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[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
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Apply
Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[PULL,49/49] docs/about/deprecated: Document RISC-V "pmu-num" deprecation
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
1 - 2 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,48/49] target/riscv: Add "pmu-mask" property to replace "pmu-num"
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,47/49] target/riscv: Use existing PMU counter mask in FDT generation
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 3 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,46/49] target/riscv: Don't assume PMU counters are continuous
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 3 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,45/49] target/riscv: Propagate error from PMU setup
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 3 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,44/49] target/riscv: cpu: Set the OpenTitan priv to 1.12.0
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,43/49] hw/ssi: ibex_spi_host: Clear the interrupt even if disabled
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,42/49] disas/riscv: Replace TABs with space
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
1 - - -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,41/49] disas/riscv: Add support for vector crypto extensions
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - - -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,40/49] disas/riscv: Add rv_codec_vror_vi for vror.vi
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
1 - - -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,39/49] disas/riscv: Add rv_fmt_vd_vs2_uimm format
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
1 - - -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,38/49] target/riscv: Move vector crypto extensions to riscv_cpu_extensions
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
1 - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,37/49] target/riscv: Expose Zvks[c|g] extnesion properties
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
1 - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,36/49] target/riscv: Add cfg properties for Zvks[c|g] extensions
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
1 - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,35/49] target/riscv: Expose Zvkn[c|g] extnesion properties
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
1 - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,34/49] target/riscv: Add cfg properties for Zvkn[c|g] extensions
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
1 - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,33/49] target/riscv: Expose Zvkb extension property
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
1 - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,32/49] target/riscv: Replace Zvbb checking by Zvkb
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,31/49] target/riscv: Add cfg property for Zvkb extension
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
1 - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,30/49] target/riscv: Expose Zvkt extension property
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
1 - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,29/49] target/riscv: Add cfg property for Zvkt extension
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
1 - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,28/49] MAINTAINERS: update mail address for Weiwei Li
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 4 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,27/49] target/riscv: correct csr_ops[CSR_MSECCFG]
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- 1 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,26/49] target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
1 - - -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,25/49] target/riscv/kvm: add zihpm reg
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,24/49] target/riscv: add zihpm extension flag for TCG
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,23/49] target/riscv/kvm: add zicntr reg
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,22/49] target/riscv: add zicntr extension flag for TCG
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,21/49] target/riscv: pmp: Ignore writes when RW=01
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,20/49] target/riscv: pmp: Clear pmp/smepmp bits on reset
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,19/49] Add epmp to extensions list and rename it to smepmp
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 2 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,18/49] target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,17/49] target/riscv: add riscv_cpu_accelerator_compatible()
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,16/49] target/riscv: handle custom props in qmp_query_cpu_model_expansion
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,15/49] target/riscv/tcg: add tcg_cpu_finalize_features()
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,14/49] qapi,risc-v: add query-cpu-model-expansion
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,13/49] target/riscv/kvm/kvm-cpu.c: add missing property getters()
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,12/49] docs/system/riscv: update 'virt' machine core limit
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,11/49] linux-user/riscv: change default cpu to 'max'
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- 1 3 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,10/49] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,09/49] target/riscv: Add M-mode virtual interrupt and IRQ filtering support.
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,08/49] target/riscv: Split interrupt logic from riscv_cpu_update_mip.
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,07/49] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,06/49] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,05/49] target/riscv: Without H-mode mask all HS mode inturrupts in mie.
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 1 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,04/49] target/riscv: rename ext_icboz to ext_zicboz
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 2 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,03/49] target/riscv: rename ext_icbom to ext_zicbom
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 2 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,02/49] target/riscv: rename ext_icsr to ext_zicsr
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 2 -
-
-
-
2023-11-07
Alistair Francis
New
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
[PULL,01/49] target/riscv: rename ext_ifencei to ext_zifencei
- - 2 -
-
-
-
2023-11-07
Alistair Francis
New