| Message ID | 20240416230437.1869024-1-dbarboza@ventanamicro.com |
|---|---|
| Headers | show |
| Series | target/riscv: set tval in breakpoints | expand |
On Wed, Apr 17, 2024 at 9:05 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > Hi, > > This new version has a change suggested by Richard in v2. No other > changes made. > > Changes from v2: > - patch 2: > - use tcg_constant_tl() instead of loading a temp and doing a > movi_tl() > - v2 link: https://lore.kernel.org/qemu-riscv/20240416194132.1843699-1-dbarboza@ventanamicro.com/ > > > Daniel Henrique Barboza (2): > target/riscv/debug: set tval=pc in breakpoint exceptions > trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu_helper.c | 1 + > target/riscv/debug.c | 3 +++ > target/riscv/insn_trans/trans_privileged.c.inc | 2 ++ > 3 files changed, 6 insertions(+) > > -- > 2.44.0 > >
Hi, This new version has a change suggested by Richard in v2. No other changes made. Changes from v2: - patch 2: - use tcg_constant_tl() instead of loading a temp and doing a movi_tl() - v2 link: https://lore.kernel.org/qemu-riscv/20240416194132.1843699-1-dbarboza@ventanamicro.com/ Daniel Henrique Barboza (2): target/riscv/debug: set tval=pc in breakpoint exceptions trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint target/riscv/cpu_helper.c | 1 + target/riscv/debug.c | 3 +++ target/riscv/insn_trans/trans_privileged.c.inc | 2 ++ 3 files changed, 6 insertions(+)