Message ID | 20221016124726.102129-1-mchitale@ventanamicro.com |
---|---|
Headers | show |
Series | RISC-V Smstateen support | expand |
On Sun, Oct 16, 2022 at 10:48 PM Mayuresh Chitale <mchitale@ventanamicro.com> wrote: > > This series adds support for the Smstateen specification which provides a > mechanism to plug the potential covert channels which are opened by extensions > that add to processor state that may not get context-switched. Currently access > to *envcfg registers and floating point(fcsr) is controlled via smstateen. > > These patches can also be found on riscv_smstateen_v11 branch at: > https://github.com/mdchitale/qemu.git > > Changes in v11: > - Rebase to latest riscv-to-apply.next > - set virt_inst_excp at the begining of decode_opc > - Add reviewed by in patch 4 > > Changes in v10: > - Add support to generate virt instruction exception after decode failure. > Use this change for smstateen fcsr failure when virt is enabled. > - Implement single write function for *smstateen1 to *smstateen3 registers. > > Changes in v9: > - Rebase to latest riscv-to-apply.next > - Add reviewed by in patches 2 and 4 > > Changes in v8: > - Rebase to latest riscv-to-apply.next > - Fix m-mode check for hstateen > - Fix return exception type for VU mode > - Improve commit description for patch3 > > Changes in v7: > - Update smstateen check as per discussion on the following issue: > https://github.com/riscv/riscv-state-enable/issues/9 > - Drop the smstateen AIA patch for now. > - Indentation and other fixes > > Changes in v6: > - Sync with latest riscv-to-apply.next > - Make separate read/write ops for m/h/s/stateen1/2/3 regs > - Add check for mstateen.staten when reading or using h/s/stateen regs > - Add smstateen fcsr check for all floating point operations > - Move knobs to enable smstateen in a separate patch. > > Changes in v5: > - Fix the order in which smstateen extension is added to the > isa_edata_arr as > described in rule #3 the comment. > > Changes in v4: > - Fix build issue with riscv32/riscv64-linux-user targets > > Changes in v3: > - Fix coding style issues > - Fix *stateen0h index calculation > > Changes in v2: > - Make h/s/envcfg bits in m/h/stateen registers as writeable by default. > > Mayuresh Chitale (5): > target/riscv: Add smstateen support > target/riscv: smstateen check for h/s/envcfg > target/riscv: generate virtual instruction exception > target/riscv: smstateen check for fcsr > target/riscv: smstateen knobs Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.c | 2 + > target/riscv/cpu.h | 4 + > target/riscv/cpu_bits.h | 37 ++ > target/riscv/csr.c | 414 +++++++++++++++++++++- > target/riscv/insn_trans/trans_rvf.c.inc | 43 ++- > target/riscv/insn_trans/trans_rvzfh.c.inc | 12 + > target/riscv/machine.c | 21 ++ > target/riscv/translate.c | 8 +- > 8 files changed, 536 insertions(+), 5 deletions(-) > > -- > 2.25.1 > >