| Message ID | 1603863010-15807-1-git-send-email-bmeng.cn@gmail.com |
|---|---|
| Headers | show |
| Series | hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box | expand |
On Tue, Oct 27, 2020 at 10:31 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Bin Meng <bin.meng@windriver.com> > > At present the DDR memory controller is not modeled, hence the factory > HSS firmware does not boot out of the box on QEMU. A modified HSS is > required per the instructions on [1]. > > This series adds the missing DDR memory controller support to PolarFire > SoC, as well as adding various misc models to support the DDR memory > initialization done by HSS. > > With this series, the unmodified HSS image can boot on QEMU out of the > box. The latest SD card image [2] released by Microchip was used for > testing which includes the pre-built U-Boot, device tree blob and Linux > kernel. The instructions on [1] have been updated to latest information. > > [1] https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_SoC_Icicle_Kit > [2] ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz > > Changes in v2: > - new patch: Document where to look at the PolarFire SoC memory maps > - change to map the reserved memory at address 0 instead of debug memory > - Increase the default memory size to 2 GiB > > Bin Meng (10): > hw/riscv: microchip_pfsoc: Document where to look at the SoC memory > maps > hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support > hw/riscv: microchip_pfsoc: Connect DDR memory controller modules > hw/misc: Add Microchip PolarFire SoC IOSCB module support > hw/riscv: microchip_pfsoc: Connect the IOSCB module > hw/misc: Add Microchip PolarFire SoC SYSREG module support > hw/riscv: microchip_pfsoc: Connect the SYSREG module > hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 > hw/riscv: microchip_pfsoc: Correct DDR memory map > hw/riscv: microchip_pfsoc: Hook the I2C1 controller Thanks! Applied to riscv-to-apply.next Alistair > > MAINTAINERS | 6 + > hw/misc/Kconfig | 9 ++ > hw/misc/mchp_pfsoc_dmc.c | 216 ++++++++++++++++++++++++++++++++ > hw/misc/mchp_pfsoc_ioscb.c | 242 ++++++++++++++++++++++++++++++++++++ > hw/misc/mchp_pfsoc_sysreg.c | 99 +++++++++++++++ > hw/misc/meson.build | 3 + > hw/riscv/Kconfig | 3 + > hw/riscv/microchip_pfsoc.c | 123 +++++++++++++++--- > include/hw/misc/mchp_pfsoc_dmc.h | 56 +++++++++ > include/hw/misc/mchp_pfsoc_ioscb.h | 50 ++++++++ > include/hw/misc/mchp_pfsoc_sysreg.h | 39 ++++++ > include/hw/riscv/microchip_pfsoc.h | 18 ++- > 12 files changed, 847 insertions(+), 17 deletions(-) > create mode 100644 hw/misc/mchp_pfsoc_dmc.c > create mode 100644 hw/misc/mchp_pfsoc_ioscb.c > create mode 100644 hw/misc/mchp_pfsoc_sysreg.c > create mode 100644 include/hw/misc/mchp_pfsoc_dmc.h > create mode 100644 include/hw/misc/mchp_pfsoc_ioscb.h > create mode 100644 include/hw/misc/mchp_pfsoc_sysreg.h > > -- > 2.7.4 > >
From: Bin Meng <bin.meng@windriver.com> At present the DDR memory controller is not modeled, hence the factory HSS firmware does not boot out of the box on QEMU. A modified HSS is required per the instructions on [1]. This series adds the missing DDR memory controller support to PolarFire SoC, as well as adding various misc models to support the DDR memory initialization done by HSS. With this series, the unmodified HSS image can boot on QEMU out of the box. The latest SD card image [2] released by Microchip was used for testing which includes the pre-built U-Boot, device tree blob and Linux kernel. The instructions on [1] have been updated to latest information. [1] https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_SoC_Icicle_Kit [2] ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz Changes in v2: - new patch: Document where to look at the PolarFire SoC memory maps - change to map the reserved memory at address 0 instead of debug memory - Increase the default memory size to 2 GiB Bin Meng (10): hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support hw/riscv: microchip_pfsoc: Connect DDR memory controller modules hw/misc: Add Microchip PolarFire SoC IOSCB module support hw/riscv: microchip_pfsoc: Connect the IOSCB module hw/misc: Add Microchip PolarFire SoC SYSREG module support hw/riscv: microchip_pfsoc: Connect the SYSREG module hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 hw/riscv: microchip_pfsoc: Correct DDR memory map hw/riscv: microchip_pfsoc: Hook the I2C1 controller MAINTAINERS | 6 + hw/misc/Kconfig | 9 ++ hw/misc/mchp_pfsoc_dmc.c | 216 ++++++++++++++++++++++++++++++++ hw/misc/mchp_pfsoc_ioscb.c | 242 ++++++++++++++++++++++++++++++++++++ hw/misc/mchp_pfsoc_sysreg.c | 99 +++++++++++++++ hw/misc/meson.build | 3 + hw/riscv/Kconfig | 3 + hw/riscv/microchip_pfsoc.c | 123 +++++++++++++++--- include/hw/misc/mchp_pfsoc_dmc.h | 56 +++++++++ include/hw/misc/mchp_pfsoc_ioscb.h | 50 ++++++++ include/hw/misc/mchp_pfsoc_sysreg.h | 39 ++++++ include/hw/riscv/microchip_pfsoc.h | 18 ++- 12 files changed, 847 insertions(+), 17 deletions(-) create mode 100644 hw/misc/mchp_pfsoc_dmc.c create mode 100644 hw/misc/mchp_pfsoc_ioscb.c create mode 100644 hw/misc/mchp_pfsoc_sysreg.c create mode 100644 include/hw/misc/mchp_pfsoc_dmc.h create mode 100644 include/hw/misc/mchp_pfsoc_ioscb.h create mode 100644 include/hw/misc/mchp_pfsoc_sysreg.h