| Message ID | 20240723-counter_delegation-v2-4-c4170a5348ca@rivosinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add RISC-V Counter delegation ISA extension support | expand |
On Wed, Jul 24, 2024 at 9:32 AM Atish Patra <atishp@rivosinc.com> wrote: > > From: Kaiwen Xue <kaiwenx@rivosinc.com> > > This adds the indirect access registers required by sscsrind/smcsrind > and the operations on them. Note that xiselect and xireg are used for > both AIA and sxcsrind, and the behavior of accessing them depends on > whether each extension is enabled and the value stored in xiselect. > > Co-developed-by: Atish Patra <atishp@rivosinc.com> > Signed-off-by: Atish Patra <atishp@rivosinc.com> > Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> > --- > target/riscv/cpu.c | 2 + > target/riscv/cpu_bits.h | 28 ++++++++- > target/riscv/cpu_cfg.h | 2 + > target/riscv/csr.c | 149 ++++++++++++++++++++++++++++++++++++++++++++++-- > 4 files changed, 175 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ebc19090b40d..ac2dce734d80 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -182,12 +182,14 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > + ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_12_0, ext_smcdeleg), > ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_12_0, ext_smcsrind), > ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), > + ISA_EXT_DATA_ENTRY(ssccfg, PRIV_VERSION_1_12_0, ext_ssccfg), Looks like these are in the wrong patch > ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), > ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), > ISA_EXT_DATA_ENTRY(sscsrind, PRIV_VERSION_1_12_0, ext_sscsrind), > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 32b068f18aa5..2a8b53a6622e 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -170,6 +170,13 @@ > #define CSR_MISELECT 0x350 > #define CSR_MIREG 0x351 > > +/* Machine Indirect Register Alias */ > +#define CSR_MIREG2 0x352 > +#define CSR_MIREG3 0x353 > +#define CSR_MIREG4 0x355 > +#define CSR_MIREG5 0x356 > +#define CSR_MIREG6 0x357 > + > /* Machine-Level Interrupts (AIA) */ > #define CSR_MTOPEI 0x35c > #define CSR_MTOPI 0xfb0 > @@ -219,6 +226,13 @@ > #define CSR_SISELECT 0x150 > #define CSR_SIREG 0x151 > > +/* Supervisor Indirect Register Alias */ > +#define CSR_SIREG2 0x152 > +#define CSR_SIREG3 0x153 > +#define CSR_SIREG4 0x155 > +#define CSR_SIREG5 0x156 > +#define CSR_SIREG6 0x157 > + > /* Supervisor-Level Interrupts (AIA) */ > #define CSR_STOPEI 0x15c > #define CSR_STOPI 0xdb0 > @@ -285,6 +299,13 @@ > #define CSR_VSISELECT 0x250 > #define CSR_VSIREG 0x251 > > +/* Virtual Supervisor Indirect Alias */ > +#define CSR_VSIREG2 0x252 > +#define CSR_VSIREG3 0x253 > +#define CSR_VSIREG4 0x255 > +#define CSR_VSIREG5 0x256 > +#define CSR_VSIREG6 0x257 > + > /* VS-Level Interrupts (H-extension with AIA) */ > #define CSR_VSTOPEI 0x25c > #define CSR_VSTOPI 0xeb0 > @@ -846,10 +867,13 @@ typedef enum RISCVException { > #define ISELECT_IMSIC_EIE63 0xff > #define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY > #define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63 > -#define ISELECT_MASK 0x1ff > +#define ISELECT_MASK_AIA 0x1ff > + > +/* MISELECT, SISELECT, and VSISELECT bits (AIA) */ > +#define ISELECT_MASK_SXCSRIND 0xfff > > /* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ > -#define ISELECT_IMSIC_TOPEI (ISELECT_MASK + 1) > +#define ISELECT_IMSIC_TOPEI (ISELECT_MASK_AIA + 1) > > /* IMSIC bits (AIA) */ > #define IMSIC_TOPEI_IID_SHIFT 16 > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index b8a5174bc871..b2be3d47c7a3 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -79,6 +79,8 @@ struct RISCVCPUConfig { > bool ext_smcntrpmf; > bool ext_smcsrind; > bool ext_sscsrind; > + bool ext_smcdeleg; > + bool ext_ssccfg; Same here Alistair > bool ext_svadu; > bool ext_svinval; > bool ext_svnapot; > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 18b9ae802b15..4ae3931f0ada 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -287,6 +287,17 @@ static RISCVException aia_any32(CPURISCVState *env, int csrno) > return any32(env, csrno); > } > > +static RISCVException csrind_any(CPURISCVState *env, int csrno) > +{ > + RISCVCPU *cpu = env_archcpu(env); > + > + if (!cpu->cfg.ext_smcsrind) { > + return RISCV_EXCP_ILLEGAL_INST; > + } > + > + return RISCV_EXCP_NONE; > +} > + > static RISCVException csrind_or_aia_any(CPURISCVState *env, int csrno) > { > if (!riscv_cpu_cfg(env)->ext_smaia && !riscv_cpu_cfg(env)->ext_smcsrind) { > @@ -370,6 +381,15 @@ static bool csrind_or_aia_extensions_present(CPURISCVState *env) > return csrind_extensions_present(env) || aia_extensions_present(env); > } > > +static RISCVException csrind_smode(CPURISCVState *env, int csrno) > +{ > + if (!csrind_extensions_present(env)) { > + return RISCV_EXCP_ILLEGAL_INST; > + } > + > + return smode(env, csrno); > +} > + > static RISCVException csrind_or_aia_smode(CPURISCVState *env, int csrno) > { > if (!csrind_or_aia_extensions_present(env)) { > @@ -398,6 +418,15 @@ static RISCVException hmode32(CPURISCVState *env, int csrno) > > } > > +static RISCVException csrind_hmode(CPURISCVState *env, int csrno) > +{ > + if (!csrind_extensions_present(env)) { > + return RISCV_EXCP_ILLEGAL_INST; > + } > + > + return hmode(env, csrno); > +} > + > static RISCVException csrind_or_aia_hmode(CPURISCVState *env, int csrno) > { > if (!csrind_or_aia_extensions_present(env)) { > @@ -2027,7 +2056,12 @@ static int csrind_xlate_vs_csrno(CPURISCVState *env, int csrno) > case CSR_SISELECT: > return CSR_VSISELECT; > case CSR_SIREG: > - return CSR_VSIREG; > + case CSR_SIREG2: > + case CSR_SIREG3: > + case CSR_SIREG4: > + case CSR_SIREG5: > + case CSR_SIREG6: > + return CSR_VSIREG + (csrno - CSR_SIREG); > default: > return csrno; > }; > @@ -2067,7 +2101,12 @@ static RISCVException rmw_xiselect(CPURISCVState *env, int csrno, > *val = *iselect; > } > > - wr_mask &= ISELECT_MASK; > + if (riscv_cpu_cfg(env)->ext_smcsrind || riscv_cpu_cfg(env)->ext_sscsrind) { > + wr_mask &= ISELECT_MASK_SXCSRIND; > + } else { > + wr_mask &= ISELECT_MASK_AIA; > + } > + > if (wr_mask) { > *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask); > } > @@ -2206,6 +2245,59 @@ done: > return RISCV_EXCP_NONE; > } > > +/* > + * rmw_xireg_csrind: Perform indirect access to xireg and xireg2-xireg6 > + * > + * Perform indirect access to xireg and xireg2-xireg6. > + * This is a generic interface for all xireg CSRs. Apart from AIA, all other > + * extension using csrind should be implemented here. > + */ > +static int rmw_xireg_csrind(CPURISCVState *env, int csrno, > + target_ulong isel, target_ulong *val, > + target_ulong new_val, target_ulong wr_mask) > +{ > + return -EINVAL; > +} > + > +static int rmw_xiregi(CPURISCVState *env, int csrno, target_ulong *val, > + target_ulong new_val, target_ulong wr_mask) > +{ > + bool virt = false; > + int ret = -EINVAL; > + target_ulong isel; > + > + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); > + if (ret != RISCV_EXCP_NONE) { > + return ret; > + } > + > + /* Translate CSR number for VS-mode */ > + csrno = csrind_xlate_vs_csrno(env, csrno); > + > + if (CSR_MIREG <= csrno && csrno <= CSR_MIREG6 && > + csrno != CSR_MIREG4 - 1) { > + isel = env->miselect; > + } else if (CSR_SIREG <= csrno && csrno <= CSR_SIREG6 && > + csrno != CSR_SIREG4 - 1) { > + isel = env->siselect; > + } else if (CSR_VSIREG <= csrno && csrno <= CSR_VSIREG6 && > + csrno != CSR_VSIREG4 - 1) { > + isel = env->vsiselect; > + virt = true; > + } else { > + goto done; > + } > + > + return rmw_xireg_csrind(env, csrno, isel, val, new_val, wr_mask); > + > +done: > + if (ret) { > + return (env->virt_enabled && virt) ? > + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; > + } > + return RISCV_EXCP_NONE; > +} > + > static RISCVException rmw_xireg(CPURISCVState *env, int csrno, > target_ulong *val, target_ulong new_val, > target_ulong wr_mask) > @@ -2238,8 +2330,21 @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno, > goto done; > }; > > + /* > + * Use the xiselect range to determine actual op on xireg. > + * > + * Since we only checked the existence of AIA or Indirect Access in the > + * predicate, we should check the existence of the exact extension when > + * we get to a specific range and return illegal instruction exception even > + * in VS-mode. > + */ > if (xiselect_aia_range(isel)) { > return rmw_xireg_aia(env, csrno, isel, val, new_val, wr_mask); > + } else if (riscv_cpu_cfg(env)->ext_smcsrind || > + riscv_cpu_cfg(env)->ext_sscsrind) { > + return rmw_xireg_csrind(env, csrno, isel, val, new_val, wr_mask); > + } else { > + return RISCV_EXCP_ILLEGAL_INST; > } > > done: > @@ -2671,7 +2776,7 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno, > * TODO: Do we need to check ssaia as well ? Can we enable ssaia without > * smaia ? > */ > - if (riscv_cpu_cfg(env)->ext_smaia) { > + if (riscv_cpu_cfg(env)->ext_smaia || riscv_cpu_cfg(env)->ext_smcsrind) { > wr_mask |= SMSTATEEN0_SVSLCT; > } > > @@ -2764,7 +2869,7 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno, > wr_mask |= SMSTATEEN0_FCSR; > } > > - if (riscv_cpu_cfg(env)->ext_ssaia) { > + if (riscv_cpu_cfg(env)->ext_ssaia || riscv_cpu_cfg(env)->ext_sscsrind) { > wr_mask |= SMSTATEEN0_SVSLCT; > } > > @@ -5180,6 +5285,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_MIREG] = { "mireg", csrind_or_aia_any, NULL, NULL, > rmw_xireg }, > > + /* Machine Indirect Register Alias */ > + [CSR_MIREG2] = { "mireg2", csrind_any, NULL, NULL, rmw_xiregi, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_MIREG3] = { "mireg3", csrind_any, NULL, NULL, rmw_xiregi, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_MIREG4] = { "mireg4", csrind_any, NULL, NULL, rmw_xiregi, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_MIREG5] = { "mireg5", csrind_any, NULL, NULL, rmw_xiregi, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_MIREG6] = { "mireg6", csrind_any, NULL, NULL, rmw_xiregi, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + > /* Machine-Level Interrupts (AIA) */ > [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, > [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi }, > @@ -5301,6 +5418,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_SIREG] = { "sireg", csrind_or_aia_smode, NULL, NULL, > rmw_xireg }, > > + /* Supervisor Indirect Register Alias */ > + [CSR_SIREG2] = { "sireg2", csrind_smode, NULL, NULL, rmw_xiregi, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_SIREG3] = { "sireg3", csrind_smode, NULL, NULL, rmw_xiregi, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_SIREG4] = { "sireg4", csrind_smode, NULL, NULL, rmw_xiregi, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_SIREG5] = { "sireg5", csrind_smode, NULL, NULL, rmw_xiregi, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_SIREG6] = { "sireg6", csrind_smode, NULL, NULL, rmw_xiregi, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + > /* Supervisor-Level Interrupts (AIA) */ > [CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei }, > [CSR_STOPI] = { "stopi", aia_smode, read_stopi }, > @@ -5383,6 +5512,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > [CSR_VSIREG] = { "vsireg", csrind_or_aia_hmode, NULL, NULL, > rmw_xireg }, > > + /* Virtual Supervisor Indirect Alias */ > + [CSR_VSIREG2] = { "vsireg2", csrind_hmode, NULL, NULL, rmw_xiregi, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSIREG3] = { "vsireg3", csrind_hmode, NULL, NULL, rmw_xiregi, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSIREG4] = { "vsireg4", csrind_hmode, NULL, NULL, rmw_xiregi, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSIREG5] = { "vsireg5", csrind_hmode, NULL, NULL, rmw_xiregi, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + [CSR_VSIREG6] = { "vsireg6", csrind_hmode, NULL, NULL, rmw_xiregi, > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > + > /* VS-Level Interrupts (H-extension with AIA) */ > [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, > [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi }, > > -- > 2.34.1 > >
On Mon, Aug 5, 2024 at 5:15 PM Alistair Francis <alistair23@gmail.com> wrote: > > On Wed, Jul 24, 2024 at 9:32 AM Atish Patra <atishp@rivosinc.com> wrote: > > > > From: Kaiwen Xue <kaiwenx@rivosinc.com> > > > > This adds the indirect access registers required by sscsrind/smcsrind > > and the operations on them. Note that xiselect and xireg are used for > > both AIA and sxcsrind, and the behavior of accessing them depends on > > whether each extension is enabled and the value stored in xiselect. > > > > Co-developed-by: Atish Patra <atishp@rivosinc.com> > > Signed-off-by: Atish Patra <atishp@rivosinc.com> > > Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com> > > --- > > target/riscv/cpu.c | 2 + > > target/riscv/cpu_bits.h | 28 ++++++++- > > target/riscv/cpu_cfg.h | 2 + > > target/riscv/csr.c | 149 ++++++++++++++++++++++++++++++++++++++++++++++-- > > 4 files changed, 175 insertions(+), 6 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index ebc19090b40d..ac2dce734d80 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -182,12 +182,14 @@ const RISCVIsaExtData isa_edata_arr[] = { > > ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), > > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > > + ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_12_0, ext_smcdeleg), > > ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > > ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_12_0, ext_smcsrind), > > ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), > > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > > ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), > > + ISA_EXT_DATA_ENTRY(ssccfg, PRIV_VERSION_1_12_0, ext_ssccfg), > > Looks like these are in the wrong patch > Yes. Thanks for pointing it out. I will fix these in the next version. > > ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), > > ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), > > ISA_EXT_DATA_ENTRY(sscsrind, PRIV_VERSION_1_12_0, ext_sscsrind), > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > > index 32b068f18aa5..2a8b53a6622e 100644 > > --- a/target/riscv/cpu_bits.h > > +++ b/target/riscv/cpu_bits.h > > @@ -170,6 +170,13 @@ > > #define CSR_MISELECT 0x350 > > #define CSR_MIREG 0x351 > > > > +/* Machine Indirect Register Alias */ > > +#define CSR_MIREG2 0x352 > > +#define CSR_MIREG3 0x353 > > +#define CSR_MIREG4 0x355 > > +#define CSR_MIREG5 0x356 > > +#define CSR_MIREG6 0x357 > > + > > /* Machine-Level Interrupts (AIA) */ > > #define CSR_MTOPEI 0x35c > > #define CSR_MTOPI 0xfb0 > > @@ -219,6 +226,13 @@ > > #define CSR_SISELECT 0x150 > > #define CSR_SIREG 0x151 > > > > +/* Supervisor Indirect Register Alias */ > > +#define CSR_SIREG2 0x152 > > +#define CSR_SIREG3 0x153 > > +#define CSR_SIREG4 0x155 > > +#define CSR_SIREG5 0x156 > > +#define CSR_SIREG6 0x157 > > + > > /* Supervisor-Level Interrupts (AIA) */ > > #define CSR_STOPEI 0x15c > > #define CSR_STOPI 0xdb0 > > @@ -285,6 +299,13 @@ > > #define CSR_VSISELECT 0x250 > > #define CSR_VSIREG 0x251 > > > > +/* Virtual Supervisor Indirect Alias */ > > +#define CSR_VSIREG2 0x252 > > +#define CSR_VSIREG3 0x253 > > +#define CSR_VSIREG4 0x255 > > +#define CSR_VSIREG5 0x256 > > +#define CSR_VSIREG6 0x257 > > + > > /* VS-Level Interrupts (H-extension with AIA) */ > > #define CSR_VSTOPEI 0x25c > > #define CSR_VSTOPI 0xeb0 > > @@ -846,10 +867,13 @@ typedef enum RISCVException { > > #define ISELECT_IMSIC_EIE63 0xff > > #define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY > > #define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63 > > -#define ISELECT_MASK 0x1ff > > +#define ISELECT_MASK_AIA 0x1ff > > + > > +/* MISELECT, SISELECT, and VSISELECT bits (AIA) */ > > +#define ISELECT_MASK_SXCSRIND 0xfff > > > > /* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ > > -#define ISELECT_IMSIC_TOPEI (ISELECT_MASK + 1) > > +#define ISELECT_IMSIC_TOPEI (ISELECT_MASK_AIA + 1) > > > > /* IMSIC bits (AIA) */ > > #define IMSIC_TOPEI_IID_SHIFT 16 > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > > index b8a5174bc871..b2be3d47c7a3 100644 > > --- a/target/riscv/cpu_cfg.h > > +++ b/target/riscv/cpu_cfg.h > > @@ -79,6 +79,8 @@ struct RISCVCPUConfig { > > bool ext_smcntrpmf; > > bool ext_smcsrind; > > bool ext_sscsrind; > > + bool ext_smcdeleg; > > + bool ext_ssccfg; > > Same here > > Alistair > > > bool ext_svadu; > > bool ext_svinval; > > bool ext_svnapot; > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 18b9ae802b15..4ae3931f0ada 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -287,6 +287,17 @@ static RISCVException aia_any32(CPURISCVState *env, int csrno) > > return any32(env, csrno); > > } > > > > +static RISCVException csrind_any(CPURISCVState *env, int csrno) > > +{ > > + RISCVCPU *cpu = env_archcpu(env); > > + > > + if (!cpu->cfg.ext_smcsrind) { > > + return RISCV_EXCP_ILLEGAL_INST; > > + } > > + > > + return RISCV_EXCP_NONE; > > +} > > + > > static RISCVException csrind_or_aia_any(CPURISCVState *env, int csrno) > > { > > if (!riscv_cpu_cfg(env)->ext_smaia && !riscv_cpu_cfg(env)->ext_smcsrind) { > > @@ -370,6 +381,15 @@ static bool csrind_or_aia_extensions_present(CPURISCVState *env) > > return csrind_extensions_present(env) || aia_extensions_present(env); > > } > > > > +static RISCVException csrind_smode(CPURISCVState *env, int csrno) > > +{ > > + if (!csrind_extensions_present(env)) { > > + return RISCV_EXCP_ILLEGAL_INST; > > + } > > + > > + return smode(env, csrno); > > +} > > + > > static RISCVException csrind_or_aia_smode(CPURISCVState *env, int csrno) > > { > > if (!csrind_or_aia_extensions_present(env)) { > > @@ -398,6 +418,15 @@ static RISCVException hmode32(CPURISCVState *env, int csrno) > > > > } > > > > +static RISCVException csrind_hmode(CPURISCVState *env, int csrno) > > +{ > > + if (!csrind_extensions_present(env)) { > > + return RISCV_EXCP_ILLEGAL_INST; > > + } > > + > > + return hmode(env, csrno); > > +} > > + > > static RISCVException csrind_or_aia_hmode(CPURISCVState *env, int csrno) > > { > > if (!csrind_or_aia_extensions_present(env)) { > > @@ -2027,7 +2056,12 @@ static int csrind_xlate_vs_csrno(CPURISCVState *env, int csrno) > > case CSR_SISELECT: > > return CSR_VSISELECT; > > case CSR_SIREG: > > - return CSR_VSIREG; > > + case CSR_SIREG2: > > + case CSR_SIREG3: > > + case CSR_SIREG4: > > + case CSR_SIREG5: > > + case CSR_SIREG6: > > + return CSR_VSIREG + (csrno - CSR_SIREG); > > default: > > return csrno; > > }; > > @@ -2067,7 +2101,12 @@ static RISCVException rmw_xiselect(CPURISCVState *env, int csrno, > > *val = *iselect; > > } > > > > - wr_mask &= ISELECT_MASK; > > + if (riscv_cpu_cfg(env)->ext_smcsrind || riscv_cpu_cfg(env)->ext_sscsrind) { > > + wr_mask &= ISELECT_MASK_SXCSRIND; > > + } else { > > + wr_mask &= ISELECT_MASK_AIA; > > + } > > + > > if (wr_mask) { > > *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask); > > } > > @@ -2206,6 +2245,59 @@ done: > > return RISCV_EXCP_NONE; > > } > > > > +/* > > + * rmw_xireg_csrind: Perform indirect access to xireg and xireg2-xireg6 > > + * > > + * Perform indirect access to xireg and xireg2-xireg6. > > + * This is a generic interface for all xireg CSRs. Apart from AIA, all other > > + * extension using csrind should be implemented here. > > + */ > > +static int rmw_xireg_csrind(CPURISCVState *env, int csrno, > > + target_ulong isel, target_ulong *val, > > + target_ulong new_val, target_ulong wr_mask) > > +{ > > + return -EINVAL; > > +} > > + > > +static int rmw_xiregi(CPURISCVState *env, int csrno, target_ulong *val, > > + target_ulong new_val, target_ulong wr_mask) > > +{ > > + bool virt = false; > > + int ret = -EINVAL; > > + target_ulong isel; > > + > > + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); > > + if (ret != RISCV_EXCP_NONE) { > > + return ret; > > + } > > + > > + /* Translate CSR number for VS-mode */ > > + csrno = csrind_xlate_vs_csrno(env, csrno); > > + > > + if (CSR_MIREG <= csrno && csrno <= CSR_MIREG6 && > > + csrno != CSR_MIREG4 - 1) { > > + isel = env->miselect; > > + } else if (CSR_SIREG <= csrno && csrno <= CSR_SIREG6 && > > + csrno != CSR_SIREG4 - 1) { > > + isel = env->siselect; > > + } else if (CSR_VSIREG <= csrno && csrno <= CSR_VSIREG6 && > > + csrno != CSR_VSIREG4 - 1) { > > + isel = env->vsiselect; > > + virt = true; > > + } else { > > + goto done; > > + } > > + > > + return rmw_xireg_csrind(env, csrno, isel, val, new_val, wr_mask); > > + > > +done: > > + if (ret) { > > + return (env->virt_enabled && virt) ? > > + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; > > + } > > + return RISCV_EXCP_NONE; > > +} > > + > > static RISCVException rmw_xireg(CPURISCVState *env, int csrno, > > target_ulong *val, target_ulong new_val, > > target_ulong wr_mask) > > @@ -2238,8 +2330,21 @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno, > > goto done; > > }; > > > > + /* > > + * Use the xiselect range to determine actual op on xireg. > > + * > > + * Since we only checked the existence of AIA or Indirect Access in the > > + * predicate, we should check the existence of the exact extension when > > + * we get to a specific range and return illegal instruction exception even > > + * in VS-mode. > > + */ > > if (xiselect_aia_range(isel)) { > > return rmw_xireg_aia(env, csrno, isel, val, new_val, wr_mask); > > + } else if (riscv_cpu_cfg(env)->ext_smcsrind || > > + riscv_cpu_cfg(env)->ext_sscsrind) { > > + return rmw_xireg_csrind(env, csrno, isel, val, new_val, wr_mask); > > + } else { > > + return RISCV_EXCP_ILLEGAL_INST; > > } > > > > done: > > @@ -2671,7 +2776,7 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno, > > * TODO: Do we need to check ssaia as well ? Can we enable ssaia without > > * smaia ? > > */ > > - if (riscv_cpu_cfg(env)->ext_smaia) { > > + if (riscv_cpu_cfg(env)->ext_smaia || riscv_cpu_cfg(env)->ext_smcsrind) { > > wr_mask |= SMSTATEEN0_SVSLCT; > > } > > > > @@ -2764,7 +2869,7 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno, > > wr_mask |= SMSTATEEN0_FCSR; > > } > > > > - if (riscv_cpu_cfg(env)->ext_ssaia) { > > + if (riscv_cpu_cfg(env)->ext_ssaia || riscv_cpu_cfg(env)->ext_sscsrind) { > > wr_mask |= SMSTATEEN0_SVSLCT; > > } > > > > @@ -5180,6 +5285,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > > [CSR_MIREG] = { "mireg", csrind_or_aia_any, NULL, NULL, > > rmw_xireg }, > > > > + /* Machine Indirect Register Alias */ > > + [CSR_MIREG2] = { "mireg2", csrind_any, NULL, NULL, rmw_xiregi, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_MIREG3] = { "mireg3", csrind_any, NULL, NULL, rmw_xiregi, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_MIREG4] = { "mireg4", csrind_any, NULL, NULL, rmw_xiregi, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_MIREG5] = { "mireg5", csrind_any, NULL, NULL, rmw_xiregi, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_MIREG6] = { "mireg6", csrind_any, NULL, NULL, rmw_xiregi, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + > > /* Machine-Level Interrupts (AIA) */ > > [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, > > [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi }, > > @@ -5301,6 +5418,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > > [CSR_SIREG] = { "sireg", csrind_or_aia_smode, NULL, NULL, > > rmw_xireg }, > > > > + /* Supervisor Indirect Register Alias */ > > + [CSR_SIREG2] = { "sireg2", csrind_smode, NULL, NULL, rmw_xiregi, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_SIREG3] = { "sireg3", csrind_smode, NULL, NULL, rmw_xiregi, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_SIREG4] = { "sireg4", csrind_smode, NULL, NULL, rmw_xiregi, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_SIREG5] = { "sireg5", csrind_smode, NULL, NULL, rmw_xiregi, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_SIREG6] = { "sireg6", csrind_smode, NULL, NULL, rmw_xiregi, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + > > /* Supervisor-Level Interrupts (AIA) */ > > [CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei }, > > [CSR_STOPI] = { "stopi", aia_smode, read_stopi }, > > @@ -5383,6 +5512,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > > [CSR_VSIREG] = { "vsireg", csrind_or_aia_hmode, NULL, NULL, > > rmw_xireg }, > > > > + /* Virtual Supervisor Indirect Alias */ > > + [CSR_VSIREG2] = { "vsireg2", csrind_hmode, NULL, NULL, rmw_xiregi, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VSIREG3] = { "vsireg3", csrind_hmode, NULL, NULL, rmw_xiregi, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VSIREG4] = { "vsireg4", csrind_hmode, NULL, NULL, rmw_xiregi, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VSIREG5] = { "vsireg5", csrind_hmode, NULL, NULL, rmw_xiregi, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + [CSR_VSIREG6] = { "vsireg6", csrind_hmode, NULL, NULL, rmw_xiregi, > > + .min_priv_ver = PRIV_VERSION_1_12_0 }, > > + > > /* VS-Level Interrupts (H-extension with AIA) */ > > [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, > > [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi }, > > > > -- > > 2.34.1 > > > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ebc19090b40d..ac2dce734d80 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -182,12 +182,14 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), + ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_12_0, ext_smcdeleg), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_12_0, ext_smcsrind), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), + ISA_EXT_DATA_ENTRY(ssccfg, PRIV_VERSION_1_12_0, ext_ssccfg), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sscsrind, PRIV_VERSION_1_12_0, ext_sscsrind), diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 32b068f18aa5..2a8b53a6622e 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -170,6 +170,13 @@ #define CSR_MISELECT 0x350 #define CSR_MIREG 0x351 +/* Machine Indirect Register Alias */ +#define CSR_MIREG2 0x352 +#define CSR_MIREG3 0x353 +#define CSR_MIREG4 0x355 +#define CSR_MIREG5 0x356 +#define CSR_MIREG6 0x357 + /* Machine-Level Interrupts (AIA) */ #define CSR_MTOPEI 0x35c #define CSR_MTOPI 0xfb0 @@ -219,6 +226,13 @@ #define CSR_SISELECT 0x150 #define CSR_SIREG 0x151 +/* Supervisor Indirect Register Alias */ +#define CSR_SIREG2 0x152 +#define CSR_SIREG3 0x153 +#define CSR_SIREG4 0x155 +#define CSR_SIREG5 0x156 +#define CSR_SIREG6 0x157 + /* Supervisor-Level Interrupts (AIA) */ #define CSR_STOPEI 0x15c #define CSR_STOPI 0xdb0 @@ -285,6 +299,13 @@ #define CSR_VSISELECT 0x250 #define CSR_VSIREG 0x251 +/* Virtual Supervisor Indirect Alias */ +#define CSR_VSIREG2 0x252 +#define CSR_VSIREG3 0x253 +#define CSR_VSIREG4 0x255 +#define CSR_VSIREG5 0x256 +#define CSR_VSIREG6 0x257 + /* VS-Level Interrupts (H-extension with AIA) */ #define CSR_VSTOPEI 0x25c #define CSR_VSTOPI 0xeb0 @@ -846,10 +867,13 @@ typedef enum RISCVException { #define ISELECT_IMSIC_EIE63 0xff #define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY #define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63 -#define ISELECT_MASK 0x1ff +#define ISELECT_MASK_AIA 0x1ff + +/* MISELECT, SISELECT, and VSISELECT bits (AIA) */ +#define ISELECT_MASK_SXCSRIND 0xfff /* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ -#define ISELECT_IMSIC_TOPEI (ISELECT_MASK + 1) +#define ISELECT_IMSIC_TOPEI (ISELECT_MASK_AIA + 1) /* IMSIC bits (AIA) */ #define IMSIC_TOPEI_IID_SHIFT 16 diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index b8a5174bc871..b2be3d47c7a3 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -79,6 +79,8 @@ struct RISCVCPUConfig { bool ext_smcntrpmf; bool ext_smcsrind; bool ext_sscsrind; + bool ext_smcdeleg; + bool ext_ssccfg; bool ext_svadu; bool ext_svinval; bool ext_svnapot; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 18b9ae802b15..4ae3931f0ada 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -287,6 +287,17 @@ static RISCVException aia_any32(CPURISCVState *env, int csrno) return any32(env, csrno); } +static RISCVException csrind_any(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu = env_archcpu(env); + + if (!cpu->cfg.ext_smcsrind) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return RISCV_EXCP_NONE; +} + static RISCVException csrind_or_aia_any(CPURISCVState *env, int csrno) { if (!riscv_cpu_cfg(env)->ext_smaia && !riscv_cpu_cfg(env)->ext_smcsrind) { @@ -370,6 +381,15 @@ static bool csrind_or_aia_extensions_present(CPURISCVState *env) return csrind_extensions_present(env) || aia_extensions_present(env); } +static RISCVException csrind_smode(CPURISCVState *env, int csrno) +{ + if (!csrind_extensions_present(env)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return smode(env, csrno); +} + static RISCVException csrind_or_aia_smode(CPURISCVState *env, int csrno) { if (!csrind_or_aia_extensions_present(env)) { @@ -398,6 +418,15 @@ static RISCVException hmode32(CPURISCVState *env, int csrno) } +static RISCVException csrind_hmode(CPURISCVState *env, int csrno) +{ + if (!csrind_extensions_present(env)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return hmode(env, csrno); +} + static RISCVException csrind_or_aia_hmode(CPURISCVState *env, int csrno) { if (!csrind_or_aia_extensions_present(env)) { @@ -2027,7 +2056,12 @@ static int csrind_xlate_vs_csrno(CPURISCVState *env, int csrno) case CSR_SISELECT: return CSR_VSISELECT; case CSR_SIREG: - return CSR_VSIREG; + case CSR_SIREG2: + case CSR_SIREG3: + case CSR_SIREG4: + case CSR_SIREG5: + case CSR_SIREG6: + return CSR_VSIREG + (csrno - CSR_SIREG); default: return csrno; }; @@ -2067,7 +2101,12 @@ static RISCVException rmw_xiselect(CPURISCVState *env, int csrno, *val = *iselect; } - wr_mask &= ISELECT_MASK; + if (riscv_cpu_cfg(env)->ext_smcsrind || riscv_cpu_cfg(env)->ext_sscsrind) { + wr_mask &= ISELECT_MASK_SXCSRIND; + } else { + wr_mask &= ISELECT_MASK_AIA; + } + if (wr_mask) { *iselect = (*iselect & ~wr_mask) | (new_val & wr_mask); } @@ -2206,6 +2245,59 @@ done: return RISCV_EXCP_NONE; } +/* + * rmw_xireg_csrind: Perform indirect access to xireg and xireg2-xireg6 + * + * Perform indirect access to xireg and xireg2-xireg6. + * This is a generic interface for all xireg CSRs. Apart from AIA, all other + * extension using csrind should be implemented here. + */ +static int rmw_xireg_csrind(CPURISCVState *env, int csrno, + target_ulong isel, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + return -EINVAL; +} + +static int rmw_xiregi(CPURISCVState *env, int csrno, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + bool virt = false; + int ret = -EINVAL; + target_ulong isel; + + ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT); + if (ret != RISCV_EXCP_NONE) { + return ret; + } + + /* Translate CSR number for VS-mode */ + csrno = csrind_xlate_vs_csrno(env, csrno); + + if (CSR_MIREG <= csrno && csrno <= CSR_MIREG6 && + csrno != CSR_MIREG4 - 1) { + isel = env->miselect; + } else if (CSR_SIREG <= csrno && csrno <= CSR_SIREG6 && + csrno != CSR_SIREG4 - 1) { + isel = env->siselect; + } else if (CSR_VSIREG <= csrno && csrno <= CSR_VSIREG6 && + csrno != CSR_VSIREG4 - 1) { + isel = env->vsiselect; + virt = true; + } else { + goto done; + } + + return rmw_xireg_csrind(env, csrno, isel, val, new_val, wr_mask); + +done: + if (ret) { + return (env->virt_enabled && virt) ? + RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST; + } + return RISCV_EXCP_NONE; +} + static RISCVException rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val, target_ulong new_val, target_ulong wr_mask) @@ -2238,8 +2330,21 @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno, goto done; }; + /* + * Use the xiselect range to determine actual op on xireg. + * + * Since we only checked the existence of AIA or Indirect Access in the + * predicate, we should check the existence of the exact extension when + * we get to a specific range and return illegal instruction exception even + * in VS-mode. + */ if (xiselect_aia_range(isel)) { return rmw_xireg_aia(env, csrno, isel, val, new_val, wr_mask); + } else if (riscv_cpu_cfg(env)->ext_smcsrind || + riscv_cpu_cfg(env)->ext_sscsrind) { + return rmw_xireg_csrind(env, csrno, isel, val, new_val, wr_mask); + } else { + return RISCV_EXCP_ILLEGAL_INST; } done: @@ -2671,7 +2776,7 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno, * TODO: Do we need to check ssaia as well ? Can we enable ssaia without * smaia ? */ - if (riscv_cpu_cfg(env)->ext_smaia) { + if (riscv_cpu_cfg(env)->ext_smaia || riscv_cpu_cfg(env)->ext_smcsrind) { wr_mask |= SMSTATEEN0_SVSLCT; } @@ -2764,7 +2869,7 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno, wr_mask |= SMSTATEEN0_FCSR; } - if (riscv_cpu_cfg(env)->ext_ssaia) { + if (riscv_cpu_cfg(env)->ext_ssaia || riscv_cpu_cfg(env)->ext_sscsrind) { wr_mask |= SMSTATEEN0_SVSLCT; } @@ -5180,6 +5285,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MIREG] = { "mireg", csrind_or_aia_any, NULL, NULL, rmw_xireg }, + /* Machine Indirect Register Alias */ + [CSR_MIREG2] = { "mireg2", csrind_any, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MIREG3] = { "mireg3", csrind_any, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MIREG4] = { "mireg4", csrind_any, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MIREG5] = { "mireg5", csrind_any, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_MIREG6] = { "mireg6", csrind_any, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* Machine-Level Interrupts (AIA) */ [CSR_MTOPEI] = { "mtopei", aia_any, NULL, NULL, rmw_xtopei }, [CSR_MTOPI] = { "mtopi", aia_any, read_mtopi }, @@ -5301,6 +5418,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_SIREG] = { "sireg", csrind_or_aia_smode, NULL, NULL, rmw_xireg }, + /* Supervisor Indirect Register Alias */ + [CSR_SIREG2] = { "sireg2", csrind_smode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_SIREG3] = { "sireg3", csrind_smode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_SIREG4] = { "sireg4", csrind_smode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_SIREG5] = { "sireg5", csrind_smode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_SIREG6] = { "sireg6", csrind_smode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* Supervisor-Level Interrupts (AIA) */ [CSR_STOPEI] = { "stopei", aia_smode, NULL, NULL, rmw_xtopei }, [CSR_STOPI] = { "stopi", aia_smode, read_stopi }, @@ -5383,6 +5512,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_VSIREG] = { "vsireg", csrind_or_aia_hmode, NULL, NULL, rmw_xireg }, + /* Virtual Supervisor Indirect Alias */ + [CSR_VSIREG2] = { "vsireg2", csrind_hmode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSIREG3] = { "vsireg3", csrind_hmode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSIREG4] = { "vsireg4", csrind_hmode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSIREG5] = { "vsireg5", csrind_hmode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + [CSR_VSIREG6] = { "vsireg6", csrind_hmode, NULL, NULL, rmw_xiregi, + .min_priv_ver = PRIV_VERSION_1_12_0 }, + /* VS-Level Interrupts (H-extension with AIA) */ [CSR_VSTOPEI] = { "vstopei", aia_hmode, NULL, NULL, rmw_xtopei }, [CSR_VSTOPI] = { "vstopi", aia_hmode, read_vstopi },