| Message ID | 20240314175704.478276-3-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: vector fixes | expand |
On Fri, Mar 15, 2024 at 3:59 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > trans_vmv_x_s, trans_vmv_s_x, trans_vfmv_f_s and trans_vfmv_s_f aren't > setting vstart = 0 after execution. This is usually done by a helper in > vector_helper.c but these functions don't use helpers. > > We'll set vstart after any potential 'over' brconds, and that will also > mandate a mark_vs_dirty() too. > > Fixes: dedc53cbc9 ("target/riscv: rvv-1.0: integer scalar move instructions") > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/insn_trans/trans_rvv.c.inc | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index e42728990e..8c16a9f5b3 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -3373,6 +3373,8 @@ static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_s *a) > vec_element_loadi(s, t1, a->rs2, 0, true); > tcg_gen_trunc_i64_tl(dest, t1); > gen_set_gpr(s, a->rd, dest); > + tcg_gen_movi_tl(cpu_vstart, 0); > + mark_vs_dirty(s); > return true; > } > return false; > @@ -3399,8 +3401,9 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) > s1 = get_gpr(s, a->rs1, EXT_NONE); > tcg_gen_ext_tl_i64(t1, s1); > vec_element_storei(s, a->rd, 0, t1); > - mark_vs_dirty(s); > gen_set_label(over); > + tcg_gen_movi_tl(cpu_vstart, 0); > + mark_vs_dirty(s); > return true; > } > return false; > @@ -3427,6 +3430,8 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) > } > > mark_fs_dirty(s); > + tcg_gen_movi_tl(cpu_vstart, 0); > + mark_vs_dirty(s); > return true; > } > return false; > @@ -3452,8 +3457,9 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) > do_nanbox(s, t1, cpu_fpr[a->rs1]); > > vec_element_storei(s, a->rd, 0, t1); > - mark_vs_dirty(s); > gen_set_label(over); > + tcg_gen_movi_tl(cpu_vstart, 0); > + mark_vs_dirty(s); > return true; > } > return false; > -- > 2.44.0 > >
On 2024/3/15 1:56, Daniel Henrique Barboza wrote: > trans_vmv_x_s, trans_vmv_s_x, trans_vfmv_f_s and trans_vfmv_s_f aren't > setting vstart = 0 after execution. This is usually done by a helper in > vector_helper.c but these functions don't use helpers. > > We'll set vstart after any potential 'over' brconds, and that will also > mandate a mark_vs_dirty() too. > > Fixes: dedc53cbc9 ("target/riscv: rvv-1.0: integer scalar move instructions") > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewd-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Zhiwei > --- > target/riscv/insn_trans/trans_rvv.c.inc | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index e42728990e..8c16a9f5b3 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -3373,6 +3373,8 @@ static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_s *a) > vec_element_loadi(s, t1, a->rs2, 0, true); > tcg_gen_trunc_i64_tl(dest, t1); > gen_set_gpr(s, a->rd, dest); > + tcg_gen_movi_tl(cpu_vstart, 0); > + mark_vs_dirty(s); > return true; > } > return false; > @@ -3399,8 +3401,9 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) > s1 = get_gpr(s, a->rs1, EXT_NONE); > tcg_gen_ext_tl_i64(t1, s1); > vec_element_storei(s, a->rd, 0, t1); > - mark_vs_dirty(s); > gen_set_label(over); > + tcg_gen_movi_tl(cpu_vstart, 0); > + mark_vs_dirty(s); > return true; > } > return false; > @@ -3427,6 +3430,8 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) > } > > mark_fs_dirty(s); > + tcg_gen_movi_tl(cpu_vstart, 0); > + mark_vs_dirty(s); > return true; > } > return false; > @@ -3452,8 +3457,9 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) > do_nanbox(s, t1, cpu_fpr[a->rs1]); > > vec_element_storei(s, a->rd, 0, t1); > - mark_vs_dirty(s); > gen_set_label(over); > + tcg_gen_movi_tl(cpu_vstart, 0); > + mark_vs_dirty(s); > return true; > } > return false;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index e42728990e..8c16a9f5b3 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3373,6 +3373,8 @@ static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_s *a) vec_element_loadi(s, t1, a->rs2, 0, true); tcg_gen_trunc_i64_tl(dest, t1); gen_set_gpr(s, a->rd, dest); + tcg_gen_movi_tl(cpu_vstart, 0); + mark_vs_dirty(s); return true; } return false; @@ -3399,8 +3401,9 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a) s1 = get_gpr(s, a->rs1, EXT_NONE); tcg_gen_ext_tl_i64(t1, s1); vec_element_storei(s, a->rd, 0, t1); - mark_vs_dirty(s); gen_set_label(over); + tcg_gen_movi_tl(cpu_vstart, 0); + mark_vs_dirty(s); return true; } return false; @@ -3427,6 +3430,8 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) } mark_fs_dirty(s); + tcg_gen_movi_tl(cpu_vstart, 0); + mark_vs_dirty(s); return true; } return false; @@ -3452,8 +3457,9 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) do_nanbox(s, t1, cpu_fpr[a->rs1]); vec_element_storei(s, a->rd, 0, t1); - mark_vs_dirty(s); gen_set_label(over); + tcg_gen_movi_tl(cpu_vstart, 0); + mark_vs_dirty(s); return true; } return false;
trans_vmv_x_s, trans_vmv_s_x, trans_vfmv_f_s and trans_vfmv_s_f aren't setting vstart = 0 after execution. This is usually done by a helper in vector_helper.c but these functions don't use helpers. We'll set vstart after any potential 'over' brconds, and that will also mandate a mark_vs_dirty() too. Fixes: dedc53cbc9 ("target/riscv: rvv-1.0: integer scalar move instructions") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/insn_trans/trans_rvv.c.inc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)