| Message ID | 20240221213140.365232-3-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: set vstart_eq_zero on mark_vs_dirty | expand |
On Thu, Feb 22, 2024 at 7:34 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > After the 'mark_vs_dirty' changes from the previous patch the 'is_store' > bool is unused in all load/store functions that were changed. Remove it. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/insn_trans/trans_rvv.c.inc | 69 ++++++++++++------------- > 1 file changed, 34 insertions(+), 35 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 7a98f1caa6..15ccebf3fc 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -609,8 +609,7 @@ typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv, > TCGv_env, TCGv_i32); > > static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, > - gen_helper_ldst_us *fn, DisasContext *s, > - bool is_store) > + gen_helper_ldst_us *fn, DisasContext *s) > { > TCGv_ptr dest, mask; > TCGv base; > @@ -673,7 +672,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew) > data = FIELD_DP32(data, VDATA, NF, a->nf); > data = FIELD_DP32(data, VDATA, VTA, s->vta); > data = FIELD_DP32(data, VDATA, VMA, s->vma); > - return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); > + return ldst_us_trans(a->rd, a->rs1, data, fn, s); > } > > static bool ld_us_check(DisasContext *s, arg_r2nfvm* a, uint8_t eew) > @@ -710,7 +709,7 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew) > data = FIELD_DP32(data, VDATA, VM, a->vm); > data = FIELD_DP32(data, VDATA, LMUL, emul); > data = FIELD_DP32(data, VDATA, NF, a->nf); > - return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); > + return ldst_us_trans(a->rd, a->rs1, data, fn, s); > } > > static bool st_us_check(DisasContext *s, arg_r2nfvm* a, uint8_t eew) > @@ -739,7 +738,7 @@ static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a, uint8_t eew) > /* Mask destination register are always tail-agnostic */ > data = FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s); > data = FIELD_DP32(data, VDATA, VMA, s->vma); > - return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); > + return ldst_us_trans(a->rd, a->rs1, data, fn, s); > } > > static bool ld_us_mask_check(DisasContext *s, arg_vlm_v *a, uint8_t eew) > @@ -756,7 +755,7 @@ static bool st_us_mask_op(DisasContext *s, arg_vsm_v *a, uint8_t eew) > /* EMUL = 1, NFIELDS = 1 */ > data = FIELD_DP32(data, VDATA, LMUL, 0); > data = FIELD_DP32(data, VDATA, NF, 1); > - return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); > + return ldst_us_trans(a->rd, a->rs1, data, fn, s); > } > > static bool st_us_mask_check(DisasContext *s, arg_vsm_v *a, uint8_t eew) > @@ -776,7 +775,7 @@ typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv, > > static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, > uint32_t data, gen_helper_ldst_stride *fn, > - DisasContext *s, bool is_store) > + DisasContext *s) > { > TCGv_ptr dest, mask; > TCGv base, stride; > @@ -823,7 +822,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) > data = FIELD_DP32(data, VDATA, NF, a->nf); > data = FIELD_DP32(data, VDATA, VTA, s->vta); > data = FIELD_DP32(data, VDATA, VMA, s->vma); > - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); > + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); > } > > static bool ld_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) > @@ -857,7 +856,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) > return false; > } > > - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); > + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); > } > > static bool st_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) > @@ -880,7 +879,7 @@ typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv, > > static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, > uint32_t data, gen_helper_ldst_index *fn, > - DisasContext *s, bool is_store) > + DisasContext *s) > { > TCGv_ptr dest, mask, index; > TCGv base; > @@ -947,7 +946,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) > data = FIELD_DP32(data, VDATA, NF, a->nf); > data = FIELD_DP32(data, VDATA, VTA, s->vta); > data = FIELD_DP32(data, VDATA, VMA, s->vma); > - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); > + return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); > } > > static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) > @@ -999,7 +998,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) > data = FIELD_DP32(data, VDATA, VM, a->vm); > data = FIELD_DP32(data, VDATA, LMUL, emul); > data = FIELD_DP32(data, VDATA, NF, a->nf); > - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); > + return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); > } > > static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) > @@ -1078,7 +1077,7 @@ typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32); > > static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf, > uint32_t width, gen_helper_ldst_whole *fn, > - DisasContext *s, bool is_store) > + DisasContext *s) > { > uint32_t evl = s->cfg_ptr->vlenb * nf / width; > TCGLabel *over = gen_new_label(); > @@ -1109,42 +1108,42 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf, > * load and store whole register instructions ignore vtype and vl setting. > * Thus, we don't need to check vill bit. (Section 7.9) > */ > -#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH, IS_STORE) \ > +#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH) \ > static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ > { \ > if (require_rvv(s) && \ > QEMU_IS_ALIGNED(a->rd, ARG_NF)) { \ > return ldst_whole_trans(a->rd, a->rs1, ARG_NF, WIDTH, \ > - gen_helper_##NAME, s, IS_STORE); \ > + gen_helper_##NAME, s); \ > } \ > return false; \ > } > > -GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1, false) > -GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2, false) > -GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4, false) > -GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8, false) > -GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1, false) > -GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2, false) > -GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4, false) > -GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8, false) > -GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1, false) > -GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2, false) > -GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4, false) > -GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8, false) > -GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1, false) > -GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2, false) > -GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4, false) > -GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8, false) > +GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1) > +GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2) > +GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4) > +GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8) > +GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1) > +GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2) > +GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4) > +GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8) > +GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1) > +GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2) > +GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4) > +GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8) > +GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1) > +GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2) > +GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4) > +GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8) > > /* > * The vector whole register store instructions are encoded similar to > * unmasked unit-stride store of elements with EEW=8. > */ > -GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1, true) > -GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1, true) > -GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1, true) > -GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1, true) > +GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1) > +GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1) > +GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1) > +GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1) > > /* > *** Vector Integer Arithmetic Instructions > -- > 2.43.2 > >
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 7a98f1caa6..15ccebf3fc 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -609,8 +609,7 @@ typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv, TCGv_env, TCGv_i32); static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, - gen_helper_ldst_us *fn, DisasContext *s, - bool is_store) + gen_helper_ldst_us *fn, DisasContext *s) { TCGv_ptr dest, mask; TCGv base; @@ -673,7 +672,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew) data = FIELD_DP32(data, VDATA, NF, a->nf); data = FIELD_DP32(data, VDATA, VTA, s->vta); data = FIELD_DP32(data, VDATA, VMA, s->vma); - return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); + return ldst_us_trans(a->rd, a->rs1, data, fn, s); } static bool ld_us_check(DisasContext *s, arg_r2nfvm* a, uint8_t eew) @@ -710,7 +709,7 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew) data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, emul); data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); + return ldst_us_trans(a->rd, a->rs1, data, fn, s); } static bool st_us_check(DisasContext *s, arg_r2nfvm* a, uint8_t eew) @@ -739,7 +738,7 @@ static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a, uint8_t eew) /* Mask destination register are always tail-agnostic */ data = FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s); data = FIELD_DP32(data, VDATA, VMA, s->vma); - return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); + return ldst_us_trans(a->rd, a->rs1, data, fn, s); } static bool ld_us_mask_check(DisasContext *s, arg_vlm_v *a, uint8_t eew) @@ -756,7 +755,7 @@ static bool st_us_mask_op(DisasContext *s, arg_vsm_v *a, uint8_t eew) /* EMUL = 1, NFIELDS = 1 */ data = FIELD_DP32(data, VDATA, LMUL, 0); data = FIELD_DP32(data, VDATA, NF, 1); - return ldst_us_trans(a->rd, a->rs1, data, fn, s, true); + return ldst_us_trans(a->rd, a->rs1, data, fn, s); } static bool st_us_mask_check(DisasContext *s, arg_vsm_v *a, uint8_t eew) @@ -776,7 +775,7 @@ typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv, static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2, uint32_t data, gen_helper_ldst_stride *fn, - DisasContext *s, bool is_store) + DisasContext *s) { TCGv_ptr dest, mask; TCGv base, stride; @@ -823,7 +822,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) data = FIELD_DP32(data, VDATA, NF, a->nf); data = FIELD_DP32(data, VDATA, VTA, s->vta); data = FIELD_DP32(data, VDATA, VMA, s->vma); - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); } static bool ld_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) @@ -857,7 +856,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) return false; } - return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); + return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s); } static bool st_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) @@ -880,7 +879,7 @@ typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv, static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t data, gen_helper_ldst_index *fn, - DisasContext *s, bool is_store) + DisasContext *s) { TCGv_ptr dest, mask, index; TCGv base; @@ -947,7 +946,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) data = FIELD_DP32(data, VDATA, NF, a->nf); data = FIELD_DP32(data, VDATA, VTA, s->vta); data = FIELD_DP32(data, VDATA, VMA, s->vma); - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false); + return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); } static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) @@ -999,7 +998,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew) data = FIELD_DP32(data, VDATA, VM, a->vm); data = FIELD_DP32(data, VDATA, LMUL, emul); data = FIELD_DP32(data, VDATA, NF, a->nf); - return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true); + return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s); } static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew) @@ -1078,7 +1077,7 @@ typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32); static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf, uint32_t width, gen_helper_ldst_whole *fn, - DisasContext *s, bool is_store) + DisasContext *s) { uint32_t evl = s->cfg_ptr->vlenb * nf / width; TCGLabel *over = gen_new_label(); @@ -1109,42 +1108,42 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf, * load and store whole register instructions ignore vtype and vl setting. * Thus, we don't need to check vill bit. (Section 7.9) */ -#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH, IS_STORE) \ +#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH) \ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ { \ if (require_rvv(s) && \ QEMU_IS_ALIGNED(a->rd, ARG_NF)) { \ return ldst_whole_trans(a->rd, a->rs1, ARG_NF, WIDTH, \ - gen_helper_##NAME, s, IS_STORE); \ + gen_helper_##NAME, s); \ } \ return false; \ } -GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1, false) -GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2, false) -GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4, false) -GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8, false) -GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1, false) -GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2, false) -GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4, false) -GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8, false) -GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1, false) -GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2, false) -GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4, false) -GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8, false) -GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1, false) -GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2, false) -GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4, false) -GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8, false) +GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1) +GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2) +GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4) +GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8) +GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1) +GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2) +GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4) +GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8) +GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1) +GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2) +GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4) +GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8) +GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1) +GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2) +GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4) +GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8) /* * The vector whole register store instructions are encoded similar to * unmasked unit-stride store of elements with EEW=8. */ -GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1, true) -GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1, true) -GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1, true) -GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1, true) +GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1) +GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1) +GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1) +GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1) /* *** Vector Integer Arithmetic Instructions