diff mbox series

[2/2] target/riscv: Raise an exception when sdtrig is turned off

Message ID 20240110040203.1920924-3-hchauhan@ventanamicro.com
State New
Headers show
Series Export debug triggers as an extension | expand

Commit Message

Himanshu Chauhan Jan. 10, 2024, 4:02 a.m. UTC 
When sdtrig is turned off by "sdtrig=false" option, raise
and illegal instruction exception on any read/write to
sdtrig CSRs.

Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
---
 target/riscv/csr.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

Comments

Alistair Francis Jan. 12, 2024, 3:33 a.m. UTC | #1 
On Wed, Jan 10, 2024 at 2:03 PM Himanshu Chauhan
<hchauhan@ventanamicro.com> wrote:
>
> When sdtrig is turned off by "sdtrig=false" option, raise
> and illegal instruction exception on any read/write to
> sdtrig CSRs.
>
> Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
> ---
>  target/riscv/csr.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index c50a33397c..b9ca016ef2 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3854,6 +3854,10 @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
>  static RISCVException read_tselect(CPURISCVState *env, int csrno,
>                                     target_ulong *val)
>  {
> +    if (!riscv_cpu_cfg(env)->ext_sdtrig) {
> +        return RISCV_EXCP_ILLEGAL_INST;
> +    }

Thanks for the patch!

You should be able to add this check to the

static RISCVException debug(CPURISCVState *env, int csrno)

function instead

Alistair

> +
>      *val = tselect_csr_read(env);
>      return RISCV_EXCP_NONE;
>  }
> @@ -3861,6 +3865,10 @@ static RISCVException read_tselect(CPURISCVState *env, int csrno,
>  static RISCVException write_tselect(CPURISCVState *env, int csrno,
>                                      target_ulong val)
>  {
> +    if (!riscv_cpu_cfg(env)->ext_sdtrig) {
> +        return RISCV_EXCP_ILLEGAL_INST;
> +    }
> +
>      tselect_csr_write(env, val);
>      return RISCV_EXCP_NONE;
>  }
> @@ -3868,6 +3876,10 @@ static RISCVException write_tselect(CPURISCVState *env, int csrno,
>  static RISCVException read_tdata(CPURISCVState *env, int csrno,
>                                   target_ulong *val)
>  {
> +    if (!riscv_cpu_cfg(env)->ext_sdtrig) {
> +        return RISCV_EXCP_ILLEGAL_INST;
> +    }
> +
>      /* return 0 in tdata1 to end the trigger enumeration */
>      if (env->trigger_cur >= RV_MAX_TRIGGERS && csrno == CSR_TDATA1) {
>          *val = 0;
> @@ -3885,6 +3897,10 @@ static RISCVException read_tdata(CPURISCVState *env, int csrno,
>  static RISCVException write_tdata(CPURISCVState *env, int csrno,
>                                    target_ulong val)
>  {
> +    if (!riscv_cpu_cfg(env)->ext_sdtrig) {
> +        return RISCV_EXCP_ILLEGAL_INST;
> +    }
> +
>      if (!tdata_available(env, csrno - CSR_TDATA1)) {
>          return RISCV_EXCP_ILLEGAL_INST;
>      }
> @@ -3896,6 +3912,10 @@ static RISCVException write_tdata(CPURISCVState *env, int csrno,
>  static RISCVException read_tinfo(CPURISCVState *env, int csrno,
>                                   target_ulong *val)
>  {
> +    if (!riscv_cpu_cfg(env)->ext_sdtrig) {
> +        return RISCV_EXCP_ILLEGAL_INST;
> +    }
> +
>      *val = tinfo_csr_read(env);
>      return RISCV_EXCP_NONE;
>  }
> --
> 2.34.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index c50a33397c..b9ca016ef2 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3854,6 +3854,10 @@  static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
 static RISCVException read_tselect(CPURISCVState *env, int csrno,
                                    target_ulong *val)
 {
+    if (!riscv_cpu_cfg(env)->ext_sdtrig) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
     *val = tselect_csr_read(env);
     return RISCV_EXCP_NONE;
 }
@@ -3861,6 +3865,10 @@  static RISCVException read_tselect(CPURISCVState *env, int csrno,
 static RISCVException write_tselect(CPURISCVState *env, int csrno,
                                     target_ulong val)
 {
+    if (!riscv_cpu_cfg(env)->ext_sdtrig) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
     tselect_csr_write(env, val);
     return RISCV_EXCP_NONE;
 }
@@ -3868,6 +3876,10 @@  static RISCVException write_tselect(CPURISCVState *env, int csrno,
 static RISCVException read_tdata(CPURISCVState *env, int csrno,
                                  target_ulong *val)
 {
+    if (!riscv_cpu_cfg(env)->ext_sdtrig) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
     /* return 0 in tdata1 to end the trigger enumeration */
     if (env->trigger_cur >= RV_MAX_TRIGGERS && csrno == CSR_TDATA1) {
         *val = 0;
@@ -3885,6 +3897,10 @@  static RISCVException read_tdata(CPURISCVState *env, int csrno,
 static RISCVException write_tdata(CPURISCVState *env, int csrno,
                                   target_ulong val)
 {
+    if (!riscv_cpu_cfg(env)->ext_sdtrig) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
     if (!tdata_available(env, csrno - CSR_TDATA1)) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
@@ -3896,6 +3912,10 @@  static RISCVException write_tdata(CPURISCVState *env, int csrno,
 static RISCVException read_tinfo(CPURISCVState *env, int csrno,
                                  target_ulong *val)
 {
+    if (!riscv_cpu_cfg(env)->ext_sdtrig) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
     *val = tinfo_csr_read(env);
     return RISCV_EXCP_NONE;
 }