| Message ID | 20231023153927.435083-4-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: zicntr/zihpm flags and disable support | expand |
On Tue, Oct 24, 2023 at 1:40 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > zihpm is the Hardware Performance Counters extension described in > chapter 12 of the unprivileged spec. It describes support for 29 > unprivileged performance counters, hpmcounter3-hpmcounter31. > > As with zicntr, QEMU already implements zihpm before it was even an > extension. zihpm is also part of the RVA22 profile, so add it to QEMU > to complement the future profile implementation. Default it to 'true' > for all existing CPUs since it was always present in the code. > > As for disabling it, there is already code in place in > target/riscv/csr.c in all predicates for these counters (ctr() and > mctr()) that disables them if cpu->cfg.pmu_num is zero. Thus, setting > cpu->cfg.pmu_num to zero if 'zihpm=false' is enough to disable the > extension. > > Set cpu->pmu_avail_ctrs mask to zero as well since this is also checked > to verify if the counters exist. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 3 +++ > target/riscv/cpu_cfg.h | 1 + > target/riscv/tcg/tcg-cpu.c | 13 +++++++++++++ > 3 files changed, 17 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 69d64ec4ca..f40da4c661 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -85,6 +85,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_zifencei), > ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), > ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), > + ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm), > ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), > ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), > ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa), > @@ -1218,6 +1219,7 @@ static void riscv_cpu_init(Object *obj) > * users disable them. > */ > RISCV_CPU(obj)->cfg.ext_zicntr = true; > + RISCV_CPU(obj)->cfg.ext_zihpm = true; > } > > typedef struct misa_ext_info { > @@ -1308,6 +1310,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false), > > MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true), > + MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true), > > MULTI_EXT_CFG_BOOL("zba", ext_zba, true), > MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true), > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 73fd4b3231..6eef4a51ea 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -69,6 +69,7 @@ struct RISCVCPUConfig { > bool ext_zicond; > bool ext_zihintntl; > bool ext_zihintpause; > + bool ext_zihpm; > bool ext_smstateen; > bool ext_sstc; > bool ext_svadu; > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index a1e4ed2e24..093bda2e75 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -549,6 +549,19 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > cpu->cfg.ext_zicntr = false; > } > > + if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { > + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { > + error_setg(errp, "zihpm requires zicsr"); > + return; > + } > + cpu->cfg.ext_zihpm = false; > + } > + > + if (!cpu->cfg.ext_zihpm) { > + cpu->cfg.pmu_num = 0; > + cpu->pmu_avail_ctrs = 0; > + } > + > /* > * Disable isa extensions based on priv spec after we > * validated and set everything we need. > -- > 2.41.0 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 69d64ec4ca..f40da4c661 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -85,6 +85,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_zifencei), ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), + ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm), ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa), @@ -1218,6 +1219,7 @@ static void riscv_cpu_init(Object *obj) * users disable them. */ RISCV_CPU(obj)->cfg.ext_zicntr = true; + RISCV_CPU(obj)->cfg.ext_zihpm = true; } typedef struct misa_ext_info { @@ -1308,6 +1310,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false), MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true), + MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true), MULTI_EXT_CFG_BOOL("zba", ext_zba, true), MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 73fd4b3231..6eef4a51ea 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -69,6 +69,7 @@ struct RISCVCPUConfig { bool ext_zicond; bool ext_zihintntl; bool ext_zihintpause; + bool ext_zihpm; bool ext_smstateen; bool ext_sstc; bool ext_svadu; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index a1e4ed2e24..093bda2e75 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -549,6 +549,19 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) cpu->cfg.ext_zicntr = false; } + if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { + if (cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zihpm))) { + error_setg(errp, "zihpm requires zicsr"); + return; + } + cpu->cfg.ext_zihpm = false; + } + + if (!cpu->cfg.ext_zihpm) { + cpu->cfg.pmu_num = 0; + cpu->pmu_avail_ctrs = 0; + } + /* * Disable isa extensions based on priv spec after we * validated and set everything we need.
zihpm is the Hardware Performance Counters extension described in chapter 12 of the unprivileged spec. It describes support for 29 unprivileged performance counters, hpmcounter3-hpmcounter31. As with zicntr, QEMU already implements zihpm before it was even an extension. zihpm is also part of the RVA22 profile, so add it to QEMU to complement the future profile implementation. Default it to 'true' for all existing CPUs since it was always present in the code. As for disabling it, there is already code in place in target/riscv/csr.c in all predicates for these counters (ctr() and mctr()) that disables them if cpu->cfg.pmu_num is zero. Thus, setting cpu->cfg.pmu_num to zero if 'zihpm=false' is enough to disable the extension. Set cpu->pmu_avail_ctrs mask to zero as well since this is also checked to verify if the counters exist. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 3 +++ target/riscv/cpu_cfg.h | 1 + target/riscv/tcg/tcg-cpu.c | 13 +++++++++++++ 3 files changed, 17 insertions(+)