Message ID | 20230728131520.110394-2-dbarboza@ventanamicro.com |
---|---|
State | New |
Headers | show |
Series | riscv: detecting user choice in TCG extensions | expand |
On Fri, Jul 28, 2023 at 9:18 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > We'll have future usage for a function where, given an offset of the > struct RISCVCPUConfig, the flag is updated to a certain val. > > Change all existing callers to use edata->ext_enable_offset instead of > 'edata'. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index b5a2266eef..644ce7a018 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -153,18 +153,17 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), > }; > > -static bool isa_ext_is_enabled(RISCVCPU *cpu, > - const struct isa_ext_data *edata) > +static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) > { > - bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; > + bool *ext_enabled = (void *)&cpu->cfg + ext_offset; > > return *ext_enabled; > } > > -static void isa_ext_update_enabled(RISCVCPU *cpu, > - const struct isa_ext_data *edata, bool en) > +static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, > + bool en) > { > - bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; > + bool *ext_enabled = (void *)&cpu->cfg + ext_offset; > > *ext_enabled = en; > } > @@ -1025,9 +1024,10 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) > > /* Force disable extensions if priv spec version does not match */ > for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { > - if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && > + if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) && > (env->priv_ver < isa_edata_arr[i].min_version)) { > - isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); > + isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset, > + false); > #ifndef CONFIG_USER_ONLY > warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx > " because privilege spec version does not match", > @@ -2271,7 +2271,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, > int i; > > for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { > - if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { > + if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) { > new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); > g_free(old); > old = new; > -- > 2.41.0 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b5a2266eef..644ce7a018 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -153,18 +153,17 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; -static bool isa_ext_is_enabled(RISCVCPU *cpu, - const struct isa_ext_data *edata) +static bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) { - bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; + bool *ext_enabled = (void *)&cpu->cfg + ext_offset; return *ext_enabled; } -static void isa_ext_update_enabled(RISCVCPU *cpu, - const struct isa_ext_data *edata, bool en) +static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, + bool en) { - bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; + bool *ext_enabled = (void *)&cpu->cfg + ext_offset; *ext_enabled = en; } @@ -1025,9 +1024,10 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) /* Force disable extensions if priv spec version does not match */ for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && + if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) && (env->priv_ver < isa_edata_arr[i].min_version)) { - isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); + isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset, + false); #ifndef CONFIG_USER_ONLY warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx " because privilege spec version does not match", @@ -2271,7 +2271,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int i; for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { + if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) { new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); g_free(old); old = new;
We'll have future usage for a function where, given an offset of the struct RISCVCPUConfig, the flag is updated to a certain val. Change all existing callers to use edata->ext_enable_offset instead of 'edata'. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)