Message ID | 20230803131424.40744-1-negge@xiph.org |
---|---|
State | New |
Headers | show |
Series | linux-user/elfload: Set V in ELF_HWCAP for RISC-V | expand |
On 8/3/23 10:14, Nathan Egge wrote: > From: "Nathan Egge" <negge@xiph.org> > > Set V bit for hwcap if misa is set. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793 > Signed-off-by: Nathan Egge <negge@xiph.org> > --- Tested with the example program described in the bug: =========== #include <sys/auxv.h> #include <stdio.h> #define ISA_V_HWCAP (1 << ('v' - 'a')) void main() { unsigned long hw_cap = getauxval(AT_HWCAP); printf("RVV %s\n", hw_cap & ISA_V_HWCAP ? "detected" : "not found"); } =========== $ ./qemu-riscv64 -cpu rv64,vext_spec=v1.0,v=true,vlen=128 -B 0x100000 ./a.out RVV detected $ ./qemu-riscv64 -cpu rv64,vext_spec=v1.0,vlen=128 -B 0x100000 ./a.out RVV not found Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Looks like 8.1 material to me. Thanks, Daniel > linux-user/elfload.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/linux-user/elfload.c b/linux-user/elfload.c > index 861ec07abc..a299ba7300 100644 > --- a/linux-user/elfload.c > +++ b/linux-user/elfload.c > @@ -1710,7 +1710,8 @@ static uint32_t get_elf_hwcap(void) > #define MISA_BIT(EXT) (1 << (EXT - 'A')) > RISCVCPU *cpu = RISCV_CPU(thread_cpu); > uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') > - | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); > + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C') > + | MISA_BIT('V'); > > return cpu->env.misa_ext & mask; > #undef MISA_BIT
On 8/3/23 07:42, Daniel Henrique Barboza wrote: > > > On 8/3/23 10:14, Nathan Egge wrote: >> From: "Nathan Egge" <negge@xiph.org> >> >> Set V bit for hwcap if misa is set. >> >> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793 >> Signed-off-by: Nathan Egge <negge@xiph.org> >> --- > > Tested with the example program described in the bug: > > =========== > #include <sys/auxv.h> > #include <stdio.h> > > #define ISA_V_HWCAP (1 << ('v' - 'a')) > > void main() { > unsigned long hw_cap = getauxval(AT_HWCAP); > printf("RVV %s\n", hw_cap & ISA_V_HWCAP ? "detected" : "not found"); > } > =========== > > $ ./qemu-riscv64 -cpu rv64,vext_spec=v1.0,v=true,vlen=128 -B 0x100000 ./a.out > RVV detected > $ ./qemu-riscv64 -cpu rv64,vext_spec=v1.0,vlen=128 -B 0x100000 ./a.out > RVV not found > > > Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Tested-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > > > Looks like 8.1 material to me. Thanks, Queued to tcg-next. r~
03.08.2023 16:14, Nathan Egge wrote: > From: "Nathan Egge" <negge@xiph.org> > > Set V bit for hwcap if misa is set. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793 > Signed-off-by: Nathan Egge <negge@xiph.org> > --- > linux-user/elfload.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/linux-user/elfload.c b/linux-user/elfload.c > index 861ec07abc..a299ba7300 100644 > --- a/linux-user/elfload.c > +++ b/linux-user/elfload.c > @@ -1710,7 +1710,8 @@ static uint32_t get_elf_hwcap(void) > #define MISA_BIT(EXT) (1 << (EXT - 'A')) > RISCVCPU *cpu = RISCV_CPU(thread_cpu); > uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') > - | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); > + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C') > + | MISA_BIT('V'); Is smells like a -stable material (incl. 7.2), is it not? Thanks, /mjt
On Tue, Aug 8, 2023 at 2:37 AM Michael Tokarev <mjt@tls.msk.ru> wrote: > > 03.08.2023 16:14, Nathan Egge wrote: > > From: "Nathan Egge" <negge@xiph.org> > > > > Set V bit for hwcap if misa is set. > > > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793 > > Signed-off-by: Nathan Egge <negge@xiph.org> > > --- > > linux-user/elfload.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/linux-user/elfload.c b/linux-user/elfload.c > > index 861ec07abc..a299ba7300 100644 > > --- a/linux-user/elfload.c > > +++ b/linux-user/elfload.c > > @@ -1710,7 +1710,8 @@ static uint32_t get_elf_hwcap(void) > > #define MISA_BIT(EXT) (1 << (EXT - 'A')) > > RISCVCPU *cpu = RISCV_CPU(thread_cpu); > > uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') > > - | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); > > + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C') > > + | MISA_BIT('V'); > > Is smells like a -stable material (incl. 7.2), is it not? I think so as well Alistair > > Thanks, > > /mjt >
diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 861ec07abc..a299ba7300 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1710,7 +1710,8 @@ static uint32_t get_elf_hwcap(void) #define MISA_BIT(EXT) (1 << (EXT - 'A')) RISCVCPU *cpu = RISCV_CPU(thread_cpu); uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') - | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C') + | MISA_BIT('V'); return cpu->env.misa_ext & mask; #undef MISA_BIT