Message ID | 20230720132424.371132-1-dbarboza@ventanamicro.com |
---|---|
Headers | show |
Series | target/riscv: add missing riscv,isa strings | expand |
On Thu, Jul 20, 2023 at 11:25 PM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > Hi, > > Found these 2 instances while working in more 8.2 material. > > I believe both are safe for freeze but I won't lose my sleep if we > decide to postpone it. I wasn't going to squeeze them into the freeze > > Daniel Henrique Barboza (2): > target/riscv/cpu.c: add zmmul isa string > target/riscv/cpu.c: add smepmp isa string Do you mind rebasing :) https://github.com/alistair23/qemu/tree/riscv-to-apply.next Alistair > > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > -- > 2.41.0 > >
On 7/23/23 23:51, Alistair Francis wrote: > On Thu, Jul 20, 2023 at 11:25 PM Daniel Henrique Barboza > <dbarboza@ventanamicro.com> wrote: >> >> Hi, >> >> Found these 2 instances while working in more 8.2 material. >> >> I believe both are safe for freeze but I won't lose my sleep if we >> decide to postpone it. > > I wasn't going to squeeze them into the freeze > >> >> Daniel Henrique Barboza (2): >> target/riscv/cpu.c: add zmmul isa string >> target/riscv/cpu.c: add smepmp isa string > > Do you mind rebasing :) > https://github.com/alistair23/qemu/tree/riscv-to-apply.next :) Thanks! Daniel > > Alistair > >> >> target/riscv/cpu.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> -- >> 2.41.0 >> >>