| Message ID | 20230717215419.124258-2-dbarboza@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: add zicntr and zihpm flags | expand |
On Tue, Jul 18, 2023 at 7:55 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > zicntr is the Base Counters and Timers extension described in chapter 12 > of the unprivileged spec. It describes support for RDCYCLE, RDTIME and > RDINSTRET. > > QEMU already implements it way before it was a discrete extension. > zicntr is part of the RVA22 profile, so let's add it to QEMU to make the > future profile implementation flag complete. > > Given than it represents an already existing feature, default it to > 'true'. Change the realize() time validation to disable it in case its > dependency (icsr) isn't present. > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 11 +++++++++++ > target/riscv/cpu_cfg.h | 1 + > 2 files changed, 12 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 9339c0241d..7ec88659be 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -85,6 +85,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), > ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), > ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), > + ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_icntr), > ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), > ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), > ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), > @@ -1291,6 +1292,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > cpu->cfg.ext_zksh = true; > } > > + if (cpu->cfg.ext_icntr && !cpu->cfg.ext_icsr) { > + cpu->cfg.ext_icntr = false; > + } > + > /* > * Disable isa extensions based on priv spec after we > * validated and set everything we need. > @@ -1778,6 +1783,12 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), > DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), > > + /* > + * Always default true - we'll disable it during > + * realize() if needed. > + */ > + DEFINE_PROP_BOOL("zicntr", RISCVCPU, cfg.ext_icntr, true), > + > DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), > DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), > DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index 2bd9510ba3..d36dc12b92 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -62,6 +62,7 @@ struct RISCVCPUConfig { > bool ext_zksh; > bool ext_zkt; > bool ext_ifencei; > + bool ext_icntr; > bool ext_icsr; > bool ext_icbom; > bool ext_icboz; > -- > 2.41.0 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9339c0241d..7ec88659be 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -85,6 +85,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), + ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_icntr), ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), @@ -1291,6 +1292,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) cpu->cfg.ext_zksh = true; } + if (cpu->cfg.ext_icntr && !cpu->cfg.ext_icsr) { + cpu->cfg.ext_icntr = false; + } + /* * Disable isa extensions based on priv spec after we * validated and set everything we need. @@ -1778,6 +1783,12 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), + /* + * Always default true - we'll disable it during + * realize() if needed. + */ + DEFINE_PROP_BOOL("zicntr", RISCVCPU, cfg.ext_icntr, true), + DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 2bd9510ba3..d36dc12b92 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -62,6 +62,7 @@ struct RISCVCPUConfig { bool ext_zksh; bool ext_zkt; bool ext_ifencei; + bool ext_icntr; bool ext_icsr; bool ext_icbom; bool ext_icboz;
zicntr is the Base Counters and Timers extension described in chapter 12 of the unprivileged spec. It describes support for RDCYCLE, RDTIME and RDINSTRET. QEMU already implements it way before it was a discrete extension. zicntr is part of the RVA22 profile, so let's add it to QEMU to make the future profile implementation flag complete. Given than it represents an already existing feature, default it to 'true'. Change the realize() time validation to disable it in case its dependency (icsr) isn't present. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- target/riscv/cpu.c | 11 +++++++++++ target/riscv/cpu_cfg.h | 1 + 2 files changed, 12 insertions(+)