Message ID | 20230706101738.460804-2-dbarboza@ventanamicro.com |
---|---|
State | New |
Headers | show |
Series | target/riscv, KVM: fixes and enhancements | expand |
On Thu, Jul 6, 2023 at 8:18 PM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > As it is today it's not possible to use '-cpu host' if the RISC-V host > has RVH enabled. This is the resulting error: > > $ ./qemu/build/qemu-system-riscv64 \ > -machine virt,accel=kvm -m 2G -smp 1 \ > -nographic -snapshot -kernel ./guest_imgs/Image \ > -initrd ./guest_imgs/rootfs_kvm_riscv64.img \ > -append "earlycon=sbi root=/dev/ram rw" \ > -cpu host > qemu-system-riscv64: H extension requires priv spec 1.12.0 > > This happens because we're checking for priv spec for all CPUs, and > since we're not setting env->priv_ver for the 'host' CPU, it's being > default to zero (i.e. PRIV_SPEC_1_10_0). > > In reality env->priv_ver does not make sense when running with the KVM > 'host' CPU. It's used to gate certain CSRs/extensions during translation > to make them unavailable if the hart declares an older spec version. It > doesn't have any other use. E.g. OpenSBI version 1.2 retrieves the spec > checking if the CSR_MCOUNTEREN, CSR_MCOUNTINHIBIT and CSR_MENVCFG CSRs > are available [1]. > > 'priv_ver' is just one example. We're doing a lot of feature validation > and setup during riscv_cpu_realize() that it doesn't apply to KVM CPUs. > Validating the feature set for those CPUs is a KVM problem that should > be handled in KVM specific code. > > The new riscv_cpu_realize_tcg() helper contains all validation logic that > are applicable to TCG CPUs only. riscv_cpu_realize() verifies if we're > running TCG and, if it's the case, proceed with the usual TCG realize() > logic. > > [1] lib/sbi/sbi_hart.c, hart_detect_features() > > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 35 +++++++++++++++++++++++++---------- > 1 file changed, 25 insertions(+), 10 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index fd647534cf..6232e6513b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -34,6 +34,7 @@ > #include "migration/vmstate.h" > #include "fpu/softfloat-helpers.h" > #include "sysemu/kvm.h" > +#include "sysemu/tcg.h" > #include "kvm_riscv.h" > #include "tcg/tcg.h" > > @@ -1386,20 +1387,12 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) > } > } > > -static void riscv_cpu_realize(DeviceState *dev, Error **errp) > +static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) > { > - CPUState *cs = CPU(dev); > RISCVCPU *cpu = RISCV_CPU(dev); > CPURISCVState *env = &cpu->env; > - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); > Error *local_err = NULL; > > - cpu_exec_realizefn(cs, &local_err); > - if (local_err != NULL) { > - error_propagate(errp, local_err); > - return; > - } > - > riscv_cpu_validate_misa_mxl(cpu, &local_err); > if (local_err != NULL) { > error_propagate(errp, local_err); > @@ -1434,7 +1427,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > > #ifndef CONFIG_USER_ONLY > - cs->tcg_cflags |= CF_PCREL; > + CPU(dev)->tcg_cflags |= CF_PCREL; > > if (cpu->cfg.ext_sstc) { > riscv_timer_init(cpu); > @@ -1447,6 +1440,28 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > } > #endif > +} > + > +static void riscv_cpu_realize(DeviceState *dev, Error **errp) > +{ > + CPUState *cs = CPU(dev); > + RISCVCPU *cpu = RISCV_CPU(dev); > + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); > + Error *local_err = NULL; > + > + cpu_exec_realizefn(cs, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > + > + if (tcg_enabled()) { > + riscv_cpu_realize_tcg(dev, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > + } > > riscv_cpu_finalize_features(cpu, &local_err); > if (local_err != NULL) { > -- > 2.41.0 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fd647534cf..6232e6513b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -34,6 +34,7 @@ #include "migration/vmstate.h" #include "fpu/softfloat-helpers.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "kvm_riscv.h" #include "tcg/tcg.h" @@ -1386,20 +1387,12 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) } } -static void riscv_cpu_realize(DeviceState *dev, Error **errp) +static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) { - CPUState *cs = CPU(dev); RISCVCPU *cpu = RISCV_CPU(dev); CPURISCVState *env = &cpu->env; - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); Error *local_err = NULL; - cpu_exec_realizefn(cs, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - return; - } - riscv_cpu_validate_misa_mxl(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); @@ -1434,7 +1427,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } #ifndef CONFIG_USER_ONLY - cs->tcg_cflags |= CF_PCREL; + CPU(dev)->tcg_cflags |= CF_PCREL; if (cpu->cfg.ext_sstc) { riscv_timer_init(cpu); @@ -1447,6 +1440,28 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } #endif +} + +static void riscv_cpu_realize(DeviceState *dev, Error **errp) +{ + CPUState *cs = CPU(dev); + RISCVCPU *cpu = RISCV_CPU(dev); + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); + Error *local_err = NULL; + + cpu_exec_realizefn(cs, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + + if (tcg_enabled()) { + riscv_cpu_realize_tcg(dev, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + } riscv_cpu_finalize_features(cpu, &local_err); if (local_err != NULL) {