Message ID | 20230707032306.4606-1-gaoshanliukou@163.com |
---|---|
State | New |
Headers | show |
Series | target/riscv KVM_RISCV_SET_TIMER macro is not configured correctly | expand |
On Fri, Jul 7, 2023 at 10:26 PM yang.zhang <gaoshanliukou@163.com> wrote: > > From: "yang.zhang" <yang.zhang@hexintek.com> > > Should set/get riscv all reg timer,i.e, time/compare/frequency/state. > > Signed-off-by:Yang Zhang <yang.zhang@hexintek.com> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1688 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/kvm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c > index 30f21453d6..0c567f668c 100644 > --- a/target/riscv/kvm.c > +++ b/target/riscv/kvm.c > @@ -99,7 +99,7 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, > > #define KVM_RISCV_SET_TIMER(cs, env, name, reg) \ > do { \ > - int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), ®); \ > + int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ > if (ret) { \ > abort(); \ > } \ > -- > 2.25.1 > >
On Fri, Jul 7, 2023 at 10:26 PM yang.zhang <gaoshanliukou@163.com> wrote: > > From: "yang.zhang" <yang.zhang@hexintek.com> > > Should set/get riscv all reg timer,i.e, time/compare/frequency/state. > > Signed-off-by:Yang Zhang <yang.zhang@hexintek.com> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1688 Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/kvm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c > index 30f21453d6..0c567f668c 100644 > --- a/target/riscv/kvm.c > +++ b/target/riscv/kvm.c > @@ -99,7 +99,7 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, > > #define KVM_RISCV_SET_TIMER(cs, env, name, reg) \ > do { \ > - int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), ®); \ > + int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ > if (ret) { \ > abort(); \ > } \ > -- > 2.25.1 > >
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 30f21453d6..0c567f668c 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -99,7 +99,7 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type, #define KVM_RISCV_SET_TIMER(cs, env, name, reg) \ do { \ - int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, time), ®); \ + int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ if (ret) { \ abort(); \ } \
From: "yang.zhang" <yang.zhang@hexintek.com> Should set/get riscv all reg timer,i.e, time/compare/frequency/state. Signed-off-by:Yang Zhang <yang.zhang@hexintek.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1688 --- target/riscv/kvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)