| Message ID | 20230518175058.2772506-3-mchitale@ventanamicro.com |
|---|---|
| State | New |
| Headers | show |
| Series | Smstateen FCSR | expand |
On Fri, May 19, 2023 at 3:51 AM Mayuresh Chitale <mchitale@ventanamicro.com> wrote: > > When misa.F is 0 tb->flags.FS field is unused and can be used to save > the current state of smstateen0.FCSR check which is needed by the > floating point translation routines. > > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_helper.c | 6 ++++++ > target/riscv/insn_trans/trans_rvf.c.inc | 7 ++++--- > 2 files changed, 10 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index b68dcfe7b6..695c189f96 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -119,6 +119,12 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, > vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); > } > > + /* With Zfinx, floating point is enabled/disabled by Smstateen. */ > + if (!riscv_has_ext(env, RVF)) { > + fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE) > + ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; > + } > + > if (cpu->cfg.debug && !icount_enabled()) { > flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); > } > diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc > index b2de4fcf3f..509a6acffe 100644 > --- a/target/riscv/insn_trans/trans_rvf.c.inc > +++ b/target/riscv/insn_trans/trans_rvf.c.inc > @@ -19,9 +19,10 @@ > */ > > #define REQUIRE_FPU do {\ > - if (ctx->mstatus_fs == EXT_STATUS_DISABLED) \ > - if (!ctx->cfg_ptr->ext_zfinx) \ > - return false; \ > + if (ctx->mstatus_fs == EXT_STATUS_DISABLED) { \ > + ctx->virt_inst_excp = ctx->virt_enabled && ctx->cfg_ptr->ext_zfinx; \ > + return false; \ > + } \ > } while (0) > > #define REQUIRE_ZFINX_OR_F(ctx) do {\ > -- > 2.34.1 >
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b68dcfe7b6..695c189f96 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -119,6 +119,12 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS)); } + /* With Zfinx, floating point is enabled/disabled by Smstateen. */ + if (!riscv_has_ext(env, RVF)) { + fs = (smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR) == RISCV_EXCP_NONE) + ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; + } + if (cpu->cfg.debug && !icount_enabled()) { flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled); } diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index b2de4fcf3f..509a6acffe 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -19,9 +19,10 @@ */ #define REQUIRE_FPU do {\ - if (ctx->mstatus_fs == EXT_STATUS_DISABLED) \ - if (!ctx->cfg_ptr->ext_zfinx) \ - return false; \ + if (ctx->mstatus_fs == EXT_STATUS_DISABLED) { \ + ctx->virt_inst_excp = ctx->virt_enabled && ctx->cfg_ptr->ext_zfinx; \ + return false; \ + } \ } while (0) #define REQUIRE_ZFINX_OR_F(ctx) do {\