| Message ID | dd7579a2a8b81632827d42a137c7f7720cc7ab5f.1653472385.git.research_trasio@irq.a4lg.com |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: Make CPU property names lowercase (w/ capitalized aliases) | expand |
On 25/05/2022 06:54, Tsukasa OI wrote: > Many CPU properties for RISC-V are in lowercase except those with > "capitalized" (or CamelCase) names: > > - Counters > - Zifencei > - Zicsr > - Zfh > - Zfhmin > - Zve32f > - Zve64f > > This commit makes lowercase names primary but keeps capitalized names > as aliases (for backward comatibility, but with deprecated status). 'compatibility' > > Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> Tested-by: Víctor Colombo <victor.colombo@eldorado.org.br> > --- > target/riscv/cpu.c | 27 ++++++++++++++++++++------- > 1 file changed, 20 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 3f21563f2d..83262586e4 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -840,6 +840,10 @@ static void riscv_cpu_init(Object *obj) > } > > static Property riscv_cpu_properties[] = { > + /* > + * Names for ISA extensions and features should be in lowercase. > + */ > + > /* Base ISA and single-letter standard extensions */ > DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), > DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), > @@ -855,11 +859,11 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), > > /* Standard unprivileged extensions */ > - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > + DEFINE_PROP_BOOL("zicsr", RISCVCPU, cfg.ext_icsr, true), > + DEFINE_PROP_BOOL("zifencei", RISCVCPU, cfg.ext_ifencei, true), > > - DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), > - DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), > + DEFINE_PROP_BOOL("zfh", RISCVCPU, cfg.ext_zfh, false), > + DEFINE_PROP_BOOL("zfhmin", RISCVCPU, cfg.ext_zfhmin, false), > DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), > DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), > DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), > @@ -884,8 +888,8 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), > DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), > > - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), > - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), > + DEFINE_PROP_BOOL("zve32f", RISCVCPU, cfg.ext_zve32f, false), > + DEFINE_PROP_BOOL("zve64f", RISCVCPU, cfg.ext_zve64f, false), > > /* Standard supervisor-level extensions */ > DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), > @@ -893,7 +897,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), > > /* Base features */ > - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > + DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true), > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), > @@ -922,6 +926,15 @@ static Property riscv_cpu_properties[] = { > /* Other options */ > DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), > > + /* Capitalized aliases (deprecated and will be removed) */ > + DEFINE_PROP("Counters", RISCVCPU, cfg.ext_counters, qdev_prop_bool, bool), > + DEFINE_PROP("Zifencei", RISCVCPU, cfg.ext_ifencei, qdev_prop_bool, bool), > + DEFINE_PROP("Zicsr", RISCVCPU, cfg.ext_icsr, qdev_prop_bool, bool), > + DEFINE_PROP("Zfh", RISCVCPU, cfg.ext_zfh, qdev_prop_bool, bool), > + DEFINE_PROP("Zfhmin", RISCVCPU, cfg.ext_zfhmin, qdev_prop_bool, bool), > + DEFINE_PROP("Zve32f", RISCVCPU, cfg.ext_zve32f, qdev_prop_bool, bool), > + DEFINE_PROP("Zve64f", RISCVCPU, cfg.ext_zve64f, qdev_prop_bool, bool), > + > DEFINE_PROP_END_OF_LIST(), > }; > > -- > 2.34.1 > > Best regards,
On 2022/05/25 21:10, Víctor Colombo wrote: > On 25/05/2022 06:54, Tsukasa OI wrote: >> Many CPU properties for RISC-V are in lowercase except those with >> "capitalized" (or CamelCase) names: >> >> - Counters >> - Zifencei >> - Zicsr >> - Zfh >> - Zfhmin >> - Zve32f >> - Zve64f >> >> This commit makes lowercase names primary but keeps capitalized names >> as aliases (for backward comatibility, but with deprecated status). > > 'compatibility' I think I somehow pressed a backspace while finalizing. I submitted v2.1 (PATCH 2/3 only) and that should be fine. https://lists.gnu.org/archive/html/qemu-riscv/2022-05/msg00417.html Thanks! Tsukasa > >> >> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> > > Tested-by: Víctor Colombo <victor.colombo@eldorado.org.br> > >> --- >> target/riscv/cpu.c | 27 ++++++++++++++++++++------- >> 1 file changed, 20 insertions(+), 7 deletions(-) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index 3f21563f2d..83262586e4 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -840,6 +840,10 @@ static void riscv_cpu_init(Object *obj) >> } >> >> static Property riscv_cpu_properties[] = { >> + /* >> + * Names for ISA extensions and features should be in lowercase. >> + */ >> + >> /* Base ISA and single-letter standard extensions */ >> DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), >> DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), >> @@ -855,11 +859,11 @@ static Property riscv_cpu_properties[] = { >> DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), >> >> /* Standard unprivileged extensions */ >> - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), >> - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), >> + DEFINE_PROP_BOOL("zicsr", RISCVCPU, cfg.ext_icsr, true), >> + DEFINE_PROP_BOOL("zifencei", RISCVCPU, cfg.ext_ifencei, true), >> >> - DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), >> - DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), >> + DEFINE_PROP_BOOL("zfh", RISCVCPU, cfg.ext_zfh, false), >> + DEFINE_PROP_BOOL("zfhmin", RISCVCPU, cfg.ext_zfhmin, false), >> DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), >> DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), >> DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), >> @@ -884,8 +888,8 @@ static Property riscv_cpu_properties[] = { >> DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), >> DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), >> >> - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), >> - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), >> + DEFINE_PROP_BOOL("zve32f", RISCVCPU, cfg.ext_zve32f, false), >> + DEFINE_PROP_BOOL("zve64f", RISCVCPU, cfg.ext_zve64f, false), >> >> /* Standard supervisor-level extensions */ >> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), >> @@ -893,7 +897,7 @@ static Property riscv_cpu_properties[] = { >> DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), >> >> /* Base features */ >> - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), >> + DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true), >> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), >> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), >> DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), >> @@ -922,6 +926,15 @@ static Property riscv_cpu_properties[] = { >> /* Other options */ >> DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, >> cfg.short_isa_string, false), >> >> + /* Capitalized aliases (deprecated and will be removed) */ >> + DEFINE_PROP("Counters", RISCVCPU, cfg.ext_counters, >> qdev_prop_bool, bool), >> + DEFINE_PROP("Zifencei", RISCVCPU, cfg.ext_ifencei, >> qdev_prop_bool, bool), >> + DEFINE_PROP("Zicsr", RISCVCPU, cfg.ext_icsr, qdev_prop_bool, bool), >> + DEFINE_PROP("Zfh", RISCVCPU, cfg.ext_zfh, qdev_prop_bool, bool), >> + DEFINE_PROP("Zfhmin", RISCVCPU, cfg.ext_zfhmin, qdev_prop_bool, >> bool), >> + DEFINE_PROP("Zve32f", RISCVCPU, cfg.ext_zve32f, qdev_prop_bool, >> bool), >> + DEFINE_PROP("Zve64f", RISCVCPU, cfg.ext_zve64f, qdev_prop_bool, >> bool), >> + >> DEFINE_PROP_END_OF_LIST(), >> }; >> >> -- >> 2.34.1 >> >> > > Best regards, >
On Thu, May 26, 2022 at 1:27 AM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: > > On 2022/05/25 21:10, Víctor Colombo wrote: > > On 25/05/2022 06:54, Tsukasa OI wrote: > >> Many CPU properties for RISC-V are in lowercase except those with > >> "capitalized" (or CamelCase) names: > >> > >> - Counters > >> - Zifencei > >> - Zicsr > >> - Zfh > >> - Zfhmin > >> - Zve32f > >> - Zve64f > >> > >> This commit makes lowercase names primary but keeps capitalized names > >> as aliases (for backward comatibility, but with deprecated status). > > > > 'compatibility' > > I think I somehow pressed a backspace while finalizing. > I submitted v2.1 (PATCH 2/3 only) and that should be fine. > > https://lists.gnu.org/archive/html/qemu-riscv/2022-05/msg00417.html Do you mind re-sending the series, it's difficult to keep track of single patch increments like this > > Thanks! > Tsukasa > > > > >> > >> Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> > > > > Tested-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > > > >> --- > >> target/riscv/cpu.c | 27 ++++++++++++++++++++------- > >> 1 file changed, 20 insertions(+), 7 deletions(-) > >> > >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > >> index 3f21563f2d..83262586e4 100644 > >> --- a/target/riscv/cpu.c > >> +++ b/target/riscv/cpu.c > >> @@ -840,6 +840,10 @@ static void riscv_cpu_init(Object *obj) > >> } > >> > >> static Property riscv_cpu_properties[] = { > >> + /* > >> + * Names for ISA extensions and features should be in lowercase. > >> + */ > >> + > >> /* Base ISA and single-letter standard extensions */ > >> DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), > >> DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), > >> @@ -855,11 +859,11 @@ static Property riscv_cpu_properties[] = { > >> DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), > >> > >> /* Standard unprivileged extensions */ > >> - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > >> - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > >> + DEFINE_PROP_BOOL("zicsr", RISCVCPU, cfg.ext_icsr, true), > >> + DEFINE_PROP_BOOL("zifencei", RISCVCPU, cfg.ext_ifencei, true), > >> > >> - DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), > >> - DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), > >> + DEFINE_PROP_BOOL("zfh", RISCVCPU, cfg.ext_zfh, false), > >> + DEFINE_PROP_BOOL("zfhmin", RISCVCPU, cfg.ext_zfhmin, false), > >> DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), > >> DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), > >> DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), > >> @@ -884,8 +888,8 @@ static Property riscv_cpu_properties[] = { > >> DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), > >> DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), > >> > >> - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), > >> - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), > >> + DEFINE_PROP_BOOL("zve32f", RISCVCPU, cfg.ext_zve32f, false), > >> + DEFINE_PROP_BOOL("zve64f", RISCVCPU, cfg.ext_zve64f, false), > >> > >> /* Standard supervisor-level extensions */ > >> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), > >> @@ -893,7 +897,7 @@ static Property riscv_cpu_properties[] = { > >> DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), > >> > >> /* Base features */ > >> - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > >> + DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true), > >> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > >> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > >> DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), > >> @@ -922,6 +926,15 @@ static Property riscv_cpu_properties[] = { > >> /* Other options */ > >> DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, > >> cfg.short_isa_string, false), > >> > >> + /* Capitalized aliases (deprecated and will be removed) */ > >> + DEFINE_PROP("Counters", RISCVCPU, cfg.ext_counters, > >> qdev_prop_bool, bool), > >> + DEFINE_PROP("Zifencei", RISCVCPU, cfg.ext_ifencei, > >> qdev_prop_bool, bool), > >> + DEFINE_PROP("Zicsr", RISCVCPU, cfg.ext_icsr, qdev_prop_bool, bool), > >> + DEFINE_PROP("Zfh", RISCVCPU, cfg.ext_zfh, qdev_prop_bool, bool), > >> + DEFINE_PROP("Zfhmin", RISCVCPU, cfg.ext_zfhmin, qdev_prop_bool, > >> bool), > >> + DEFINE_PROP("Zve32f", RISCVCPU, cfg.ext_zve32f, qdev_prop_bool, > >> bool), > >> + DEFINE_PROP("Zve64f", RISCVCPU, cfg.ext_zve64f, qdev_prop_bool, > >> bool), > >> + > >> DEFINE_PROP_END_OF_LIST(), > >> }; > >> > >> -- > >> 2.34.1 > >> > >> > > > > Best regards, > > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3f21563f2d..83262586e4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -840,6 +840,10 @@ static void riscv_cpu_init(Object *obj) } static Property riscv_cpu_properties[] = { + /* + * Names for ISA extensions and features should be in lowercase. + */ + /* Base ISA and single-letter standard extensions */ DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), @@ -855,11 +859,11 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), /* Standard unprivileged extensions */ - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), + DEFINE_PROP_BOOL("zicsr", RISCVCPU, cfg.ext_icsr, true), + DEFINE_PROP_BOOL("zifencei", RISCVCPU, cfg.ext_ifencei, true), - DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), - DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), + DEFINE_PROP_BOOL("zfh", RISCVCPU, cfg.ext_zfh, false), + DEFINE_PROP_BOOL("zfhmin", RISCVCPU, cfg.ext_zfhmin, false), DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), @@ -884,8 +888,8 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), + DEFINE_PROP_BOOL("zve32f", RISCVCPU, cfg.ext_zve32f, false), + DEFINE_PROP_BOOL("zve64f", RISCVCPU, cfg.ext_zve64f, false), /* Standard supervisor-level extensions */ DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), @@ -893,7 +897,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), /* Base features */ - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), + DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), @@ -922,6 +926,15 @@ static Property riscv_cpu_properties[] = { /* Other options */ DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), + /* Capitalized aliases (deprecated and will be removed) */ + DEFINE_PROP("Counters", RISCVCPU, cfg.ext_counters, qdev_prop_bool, bool), + DEFINE_PROP("Zifencei", RISCVCPU, cfg.ext_ifencei, qdev_prop_bool, bool), + DEFINE_PROP("Zicsr", RISCVCPU, cfg.ext_icsr, qdev_prop_bool, bool), + DEFINE_PROP("Zfh", RISCVCPU, cfg.ext_zfh, qdev_prop_bool, bool), + DEFINE_PROP("Zfhmin", RISCVCPU, cfg.ext_zfhmin, qdev_prop_bool, bool), + DEFINE_PROP("Zve32f", RISCVCPU, cfg.ext_zve32f, qdev_prop_bool, bool), + DEFINE_PROP("Zve64f", RISCVCPU, cfg.ext_zve64f, qdev_prop_bool, bool), + DEFINE_PROP_END_OF_LIST(), };
Many CPU properties for RISC-V are in lowercase except those with "capitalized" (or CamelCase) names: - Counters - Zifencei - Zicsr - Zfh - Zfhmin - Zve32f - Zve64f This commit makes lowercase names primary but keeps capitalized names as aliases (for backward comatibility, but with deprecated status). Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> --- target/riscv/cpu.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-)