| Message ID | 91633f8349253656dd08bc8dc36498a9c7538b10.1652583332.git.research_trasio@irq.a4lg.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/5] target/riscv: Fix coding style on "G" expansion | expand |
On 14/05/2022 23:56, Tsukasa OI wrote: > [E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você possa confirmar o remetente e saber que o conteúdo é seguro. Em caso de e-mail suspeito entre imediatamente em contato com o DTI. > > Because ext_? members are boolean variables, operator `&&' should be > used instead of `&'. > > Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> > --- > target/riscv/cpu.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ccacdee215..00bf26ec8b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -596,8 +596,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > return; > } > > - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & > - cpu->cfg.ext_a & cpu->cfg.ext_f & > + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && > + cpu->cfg.ext_a && cpu->cfg.ext_f && > cpu->cfg.ext_d)) { > warn_report("Setting G will also set IMAFD"); > cpu->cfg.ext_i = true; > -- > 2.34.1 > > Sorry, looks like I mistakenly reviewed v1 earlier Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br>
On Sun, May 15, 2022 at 12:56 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: > > Because ext_? members are boolean variables, operator `&&' should be > used instead of `&'. > > Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ccacdee215..00bf26ec8b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -596,8 +596,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > return; > } > > - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & > - cpu->cfg.ext_a & cpu->cfg.ext_f & > + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && > + cpu->cfg.ext_a && cpu->cfg.ext_f && > cpu->cfg.ext_d)) { > warn_report("Setting G will also set IMAFD"); > cpu->cfg.ext_i = true; > -- > 2.34.1 >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ccacdee215..00bf26ec8b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -596,8 +596,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & - cpu->cfg.ext_a & cpu->cfg.ext_f & + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && + cpu->cfg.ext_a && cpu->cfg.ext_f && cpu->cfg.ext_d)) { warn_report("Setting G will also set IMAFD"); cpu->cfg.ext_i = true;
Because ext_? members are boolean variables, operator `&&' should be used instead of `&'. Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com> --- target/riscv/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)