diff mbox series

[v5,7/7] target/riscv: add a MAINTAINERS entry for XVentanaCondOps

Message ID 20220131110201.2303275-8-philipp.tomsich@vrull.eu
State New
Headers show
Series target/riscv: Add XVentanaCondOps and supporting infrastructure changes | expand

Commit Message

Philipp Tomsich Jan. 31, 2022, 11:02 a.m. UTC
The XVentanaCondOps extension is supported by VRULL on behalf of the
Ventana Micro.  Add myself as a point-of-contact.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

---

(no changes since v3)

Changes in v3:
- add a MAINTAINERS entry for XVentanaCondOps

 MAINTAINERS | 7 +++++++
 1 file changed, 7 insertions(+)

Comments

Alistair Francis Feb. 1, 2022, 3:10 a.m. UTC | #1
On Mon, Jan 31, 2022 at 9:24 PM Philipp Tomsich
<philipp.tomsich@vrull.eu> wrote:
>
> The XVentanaCondOps extension is supported by VRULL on behalf of the
> Ventana Micro.  Add myself as a point-of-contact.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - add a MAINTAINERS entry for XVentanaCondOps
>
>  MAINTAINERS | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index b43344fa98..2e0b2ae947 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -286,6 +286,13 @@ F: include/hw/riscv/
>  F: linux-user/host/riscv32/
>  F: linux-user/host/riscv64/
>
> +RISC-V XVentanaCondOps extension
> +M: Philipp Tomsich <philipp.tomsich@vrull.eu>
> +L: qemu-riscv@nongnu.org
> +S: Supported
> +F: target/riscv/XVentanaCondOps.decode
> +F: target/riscv/insn_trans/trans_xventanacondops.c.inc
> +
>  RENESAS RX CPUs
>  R: Yoshinori Sato <ysato@users.sourceforge.jp>
>  S: Orphan
> --
> 2.33.1
>
>
diff mbox series

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index b43344fa98..2e0b2ae947 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -286,6 +286,13 @@  F: include/hw/riscv/
 F: linux-user/host/riscv32/
 F: linux-user/host/riscv64/
 
+RISC-V XVentanaCondOps extension
+M: Philipp Tomsich <philipp.tomsich@vrull.eu>
+L: qemu-riscv@nongnu.org
+S: Supported
+F: target/riscv/XVentanaCondOps.decode
+F: target/riscv/insn_trans/trans_xventanacondops.c.inc
+
 RENESAS RX CPUs
 R: Yoshinori Sato <ysato@users.sourceforge.jp>
 S: Orphan