diff mbox series

[15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device

Message ID 1591625864-31494-16-git-send-email-bmeng.cn@gmail.com
State New
Headers show
Series hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support | expand

Commit Message

Bin Meng June 8, 2020, 2:17 p.m. UTC 
From: Bin Meng <bin.meng@windriver.com>

It is enough to simply map the SiFive FU540 DDR memory controller
into the MMIO space using create_unimplemented_device(), to make
the upstream U-Boot v2020.07 DDR memory initialization codes happy.

Note we do not generate device tree fragment for the DDR memory
controller. Since the controller data in device tree consumes a
very large space (see fu540-hifive-unleashed-a00-ddr.dtsi in the
U-Boot source), and it is only needed by U-Boot SPL but not any
operating system, we choose not to generate the fragment here.
This also means when testing with U-Boot SPL, the device tree has
to come from U-Boot SPL itself, but not the one generated by QEMU
on the fly. The memory has to be set to 8GiB to match the real
HiFive Unleashed board when invoking QEMU (-m 8G).

With this commit, QEMU can boot U-Boot SPL built for SiFive FU540
all the way up to loading U-Boot proper from MMC:

$ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -m 8G -bios u-boot-spl.bin

U-Boot SPL 2020.07-rc3-00208-g88bd5b1 (Jun 08 2020 - 20:16:10 +0800)
Trying to boot from MMC1
Unhandled exception: Load access fault
EPC: 0000000008009be6 TVAL: 0000000010050014

The above exception is expected because QSPI is unsupported yet.

Signed-off-by: Bin Meng <bin.meng@windriver.com>

---

 hw/riscv/sifive_u.c         | 4 ++++
 include/hw/riscv/sifive_u.h | 1 +
 2 files changed, 5 insertions(+)

Comments

Alistair Francis June 15, 2020, 7:20 p.m. UTC | #1 
On Mon, Jun 8, 2020 at 7:29 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> It is enough to simply map the SiFive FU540 DDR memory controller
> into the MMIO space using create_unimplemented_device(), to make
> the upstream U-Boot v2020.07 DDR memory initialization codes happy.
>
> Note we do not generate device tree fragment for the DDR memory
> controller. Since the controller data in device tree consumes a
> very large space (see fu540-hifive-unleashed-a00-ddr.dtsi in the
> U-Boot source), and it is only needed by U-Boot SPL but not any
> operating system, we choose not to generate the fragment here.
> This also means when testing with U-Boot SPL, the device tree has
> to come from U-Boot SPL itself, but not the one generated by QEMU
> on the fly. The memory has to be set to 8GiB to match the real
> HiFive Unleashed board when invoking QEMU (-m 8G).
>
> With this commit, QEMU can boot U-Boot SPL built for SiFive FU540
> all the way up to loading U-Boot proper from MMC:
>
> $ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -m 8G -bios u-boot-spl.bin
>
> U-Boot SPL 2020.07-rc3-00208-g88bd5b1 (Jun 08 2020 - 20:16:10 +0800)
> Trying to boot from MMC1
> Unhandled exception: Load access fault
> EPC: 0000000008009be6 TVAL: 0000000010050014
>
> The above exception is expected because QSPI is unsupported yet.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> ---
>
>  hw/riscv/sifive_u.c         | 4 ++++
>  include/hw/riscv/sifive_u.h | 1 +
>  2 files changed, 5 insertions(+)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index c94ff6f..7923df4 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -82,6 +82,7 @@ static const struct MemmapEntry {
>      [SIFIVE_U_OTP] =      { 0x10070000,     0x1000 },
>      [SIFIVE_U_GEM] =      { 0x10090000,     0x2000 },
>      [SIFIVE_U_GEM_MGMT] = { 0x100a0000,     0x1000 },
> +    [SIFIVE_U_DMC] =      { 0x100b0000,    0x10000 },
>      [SIFIVE_U_FLASH0] =   { 0x20000000, 0x10000000 },
>      [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },
>  };
> @@ -733,6 +734,9 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
>
>      create_unimplemented_device("riscv.sifive.u.gem-mgmt",
>          memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
> +
> +    create_unimplemented_device("riscv.sifive.u.dmc",
> +        memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
>  }
>
>  static Property sifive_u_soc_props[] = {
> diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
> index 5d80f91..3e33646 100644
> --- a/include/hw/riscv/sifive_u.h
> +++ b/include/hw/riscv/sifive_u.h
> @@ -78,6 +78,7 @@ enum {
>      SIFIVE_U_UART1,
>      SIFIVE_U_GPIO,
>      SIFIVE_U_OTP,
> +    SIFIVE_U_DMC,
>      SIFIVE_U_FLASH0,
>      SIFIVE_U_DRAM,
>      SIFIVE_U_GEM,
> --
> 2.7.4
>
>
diff mbox series

Patch

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index c94ff6f..7923df4 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -82,6 +82,7 @@  static const struct MemmapEntry {
     [SIFIVE_U_OTP] =      { 0x10070000,     0x1000 },
     [SIFIVE_U_GEM] =      { 0x10090000,     0x2000 },
     [SIFIVE_U_GEM_MGMT] = { 0x100a0000,     0x1000 },
+    [SIFIVE_U_DMC] =      { 0x100b0000,    0x10000 },
     [SIFIVE_U_FLASH0] =   { 0x20000000, 0x10000000 },
     [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },
 };
@@ -733,6 +734,9 @@  static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
 
     create_unimplemented_device("riscv.sifive.u.gem-mgmt",
         memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
+
+    create_unimplemented_device("riscv.sifive.u.dmc",
+        memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
 }
 
 static Property sifive_u_soc_props[] = {
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 5d80f91..3e33646 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -78,6 +78,7 @@  enum {
     SIFIVE_U_UART1,
     SIFIVE_U_GPIO,
     SIFIVE_U_OTP,
+    SIFIVE_U_DMC,
     SIFIVE_U_FLASH0,
     SIFIVE_U_DRAM,
     SIFIVE_U_GEM,