[v5,08/22] RISC-V: KVM: Fix the initial sample period value

Message ID	20240403080452.1007601-9-atishp@rivosinc.com
State	Changes Requested
Headers	show Return-Path: <kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org> From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Ajay Kaher <akaher@vmware.com>, Alexandre Ghiti <alexghiti@rivosinc.com>, Alexey Makhalov <amakhalov@vmware.com>, Andrew Jones <ajones@ventanamicro.com>, Anup Patel <anup@brainfault.org>, Conor Dooley <conor.dooley@microchip.com>, Juergen Gross <jgross@suse.com>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, Paul Walmsley <paul.walmsley@sifive.com>, Shuah Khan <shuah@kernel.org>, virtualization@lists.linux.dev, VMware PV-Drivers Reviewers <pv-drivers@vmware.com>, Will Deacon <will@kernel.org>, x86@kernel.org Subject: [PATCH v5 08/22] RISC-V: KVM: Fix the initial sample period value Date: Wed, 3 Apr 2024 01:04:37 -0700 Message-Id: <20240403080452.1007601-9-atishp@rivosinc.com> In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com> References: <20240403080452.1007601-1-atishp@rivosinc.com> MIME-Version: 1.0 preview: The initial sample period value when counter value is not assigned should be set to maximum value supported by the counter width. Otherwise, it may result in spurious interrupts. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/kvm/vcpu_pmu.c \| 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Content analysis details: (0.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:62f listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kvm-riscv" <kvm-riscv-bounces@lists.infradead.org> Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org
Series	RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest \| expand [v5,00/22] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest [v5,01/22] RISC-V: Fix the typo in Scountovf CSR name [v5,02/22] RISC-V: Add FIRMWARE_READ_HI definition [v5,03/22] drivers/perf: riscv: Read upper bits of a firmware counter [v5,04/22] drivers/perf: riscv: Use BIT macro for shifting operations [v5,05/22] RISC-V: Add SBI PMU snapshot definitions [v5,06/22] drivers/perf: riscv: Implement SBI PMU snapshot function [v5,07/22] drivers/perf: riscv: Fix counter mask iteration for RV32 [v5,08/22] RISC-V: KVM: Fix the initial sample period value [v5,09/22] RISC-V: KVM: Rename the SBI_STA_SHMEM_DISABLE to a generic name [v5,10/22] RISC-V: KVM: No need to update the counter value during reset [v5,11/22] RISC-V: KVM: No need to exit to the user space if perf event failed [v5,12/22] RISC-V: KVM: Implement SBI PMU Snapshot feature [v5,13/22] RISC-V: KVM: Add perf sampling support for guests [v5,14/22] RISC-V: KVM: Support 64 bit firmware counters on RV32 [v5,15/22] RISC-V: KVM: Improve firmware counter read function [v5,16/22] KVM: riscv: selftests: Move sbi definitions to its own header file [v5,17/22] KVM: riscv: selftests: Add helper functions for extension checks [v5,18/22] KVM: riscv: selftests: Add Sscofpmf to get-reg-list test [v5,19/22] KVM: riscv: selftests: Add SBI PMU extension definitions [v5,20/22] KVM: riscv: selftests: Add SBI PMU selftest [v5,21/22] KVM: riscv: selftests: Add a test for PMU snapshot functionality [v5,22/22] KVM: riscv: selftests: Add a test for counter overflow

Message ID

20240403080452.1007601-9-atishp@rivosinc.com

State

Changes Requested

Headers

From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
	Ajay Kaher <akaher@vmware.com>,
	Alexandre Ghiti <alexghiti@rivosinc.com>,
	Alexey Makhalov <amakhalov@vmware.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Anup Patel <anup@brainfault.org>,
	Conor Dooley <conor.dooley@microchip.com>,
	Juergen Gross <jgross@suse.com>,
	kvm-riscv@lists.infradead.org,
	kvm@vger.kernel.org,
	linux-kselftest@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Mark Rutland <mark.rutland@arm.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Shuah Khan <shuah@kernel.org>,
	virtualization@lists.linux.dev,
	VMware PV-Drivers Reviewers <pv-drivers@vmware.com>,
	Will Deacon <will@kernel.org>,
	x86@kernel.org
Subject: [PATCH v5 08/22] RISC-V: KVM: Fix the initial sample period value
Date: Wed,  3 Apr 2024 01:04:37 -0700
Message-Id: <20240403080452.1007601-9-atishp@rivosinc.com>
In-Reply-To: <20240403080452.1007601-1-atishp@rivosinc.com>
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Series

RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest | expand

Commit Message

Atish Kumar Patra April 3, 2024, 8:04 a.m. UTC

The initial sample period value when counter value is not assigned
should be set to maximum value supported by the counter width.
Otherwise, it may result in spurious interrupts.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/kvm/vcpu_pmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Andrew Jones April 4, 2024, 11:57 a.m. UTC | #1

On Wed, Apr 03, 2024 at 01:04:37AM -0700, Atish Patra wrote:
> The initial sample period value when counter value is not assigned
> should be set to maximum value supported by the counter width.
> Otherwise, it may result in spurious interrupts.
> 
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
>  arch/riscv/kvm/vcpu_pmu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c
> index 86391a5061dd..cee1b9ca4ec4 100644
> --- a/arch/riscv/kvm/vcpu_pmu.c
> +++ b/arch/riscv/kvm/vcpu_pmu.c
> @@ -39,7 +39,7 @@ static u64 kvm_pmu_get_sample_period(struct kvm_pmc *pmc)
>  	u64 sample_period;
>  
>  	if (!pmc->counter_val)
> -		sample_period = counter_val_mask + 1;
> +		sample_period = counter_val_mask;
>  	else
>  		sample_period = (-pmc->counter_val) & counter_val_mask;
>  
> -- 
> 2.34.1
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

diff --git a/arch/riscv/kvm/vcpu_pmu.c b/arch/riscv/kvm/vcpu_pmu.c
index 86391a5061dd..cee1b9ca4ec4 100644
--- a/arch/riscv/kvm/vcpu_pmu.c
+++ b/arch/riscv/kvm/vcpu_pmu.c
@@ -39,7 +39,7 @@  static u64 kvm_pmu_get_sample_period(struct kvm_pmc *pmc)
 	u64 sample_period;
 
 	if (!pmc->counter_val)
-		sample_period = counter_val_mask + 1;
+		sample_period = counter_val_mask;
 	else
 		sample_period = (-pmc->counter_val) & counter_val_mask;

[v5,08/22] RISC-V: KVM: Fix the initial sample period value

Commit Message

Comments

Patch