Show patches with: Submitter = Atish Patra       |    State = Action Required       |    Archived = No       |   67 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[5/5] RISC-V: KVM: Remove the boot time enabling of hstateen bits Enable hstateen bits lazily for the KVM RISC-V Guests - - - - --- 2025-05-05 Atish Patra New
[4/5] RISC-V: KVM: Enable envcfg and sstateen bits lazily Enable hstateen bits lazily for the KVM RISC-V Guests - - - - --- 2025-05-05 Atish Patra New
[3/5] RISC-V: KVM: Support lazy enabling of siselect and aia bits Enable hstateen bits lazily for the KVM RISC-V Guests - - - - --- 2025-05-05 Atish Patra New
[2/5] RISC-V: KVM: Add a hstateen lazy enabler helper function Enable hstateen bits lazily for the KVM RISC-V Guests - - - - --- 2025-05-05 Atish Patra New
[1/5] RISC-V: KVM: Lazy enable hstateen IMSIC & ISEL bit Enable hstateen bits lazily for the KVM RISC-V Guests - - - - --- 2025-05-05 Atish Patra New
MAINTAINERS: Update Atish's email address MAINTAINERS: Update Atish's email address - - - - --- 2025-05-05 Atish Patra New
RISC-V: KVM: Remove experimental tag for RISC-V RISC-V: KVM: Remove experimental tag for RISC-V - - - - --- 2025-05-05 Atish Patra New
[v3,3/3] KVM: riscv: selftests: Add vector extension tests RISC-V KVM selftests improvements - - 2 - --- 2025-04-30 Atish Patra New
[v3,2/3] KVM: riscv: selftests: Decode stval to identify exact exception type RISC-V KVM selftests improvements - - 2 - --- 2025-04-30 Atish Patra New
[v3,1/3] KVM: riscv: selftests: Align the trap information wiht pt_regs RISC-V KVM selftests improvements - - 1 - --- 2025-04-30 Atish Patra New
[v2,3/3] KVM: riscv: selftests: Add vector extension tests RISC-V KVM selftests improvements - - 2 - --- 2025-04-30 Atish Patra New
[v2,2/3] KVM: riscv: selftests: Decode stval to identify exact exception type RISC-V KVM selftests improvements - - 2 - --- 2025-04-30 Atish Patra New
[v2,1/3] KVM: riscv: selftests: Align the trap information wiht pt_regs RISC-V KVM selftests improvements - - 1 - --- 2025-04-30 Atish Patra New
[v5,21/21] Sync empty-pmu-events.c with autogenerated one Add Counter delegation ISA extension support - - - - --- 2025-03-27 Atish Patra New
[v5,20/21] tools/perf: Pass the Counter constraint values in the pmu events Add Counter delegation ISA extension support - - - - --- 2025-03-27 Atish Patra New
[v5,19/21] tools/perf: Support event code for arch standard events Add Counter delegation ISA extension support - - - - --- 2025-03-27 Atish Patra New
[v5,18/21] RISC-V: perf: Add Qemu virt machine events Add Counter delegation ISA extension support - - - - --- 2025-03-27 Atish Patra New
[v5,17/21] RISC-V: perf: Add legacy event encodings via sysfs Add Counter delegation ISA extension support - - - - --- 2025-03-27 Atish Patra New
[v5,16/21] RISC-V: perf: Use config2/vendor table for event to counter mapping Add Counter delegation ISA extension support - - - - --- 2025-03-27 Atish Patra New
[v5,15/21] RISC-V: perf: Skip PMU SBI extension when not implemented Add Counter delegation ISA extension support - - - - --- 2025-03-27 Atish Patra New
[v5,14/21] RISC-V: perf: Implement supervisor counter delegation support Add Counter delegation ISA extension support - - - - --- 2025-03-27 Atish Patra New
[v5,13/21] RISC-V: perf: Add a mechanism to defined legacy event encoding Add Counter delegation ISA extension support - - - - --- 2025-03-27 Atish Patra New
[v5,12/21] RISC-V: perf: Modify the counter discovery mechanism Add Counter delegation ISA extension support - - - - --- 2025-03-27 Atish Patra New
[v5,11/21] RISC-V: perf: Restructure the SBI PMU code Add Counter delegation ISA extension support - - 1 - --- 2025-03-27 Atish Patra New
[v5,10/21] dt-bindings: riscv: add Counter delegation ISA extensions description Add Counter delegation ISA extension support 1 - - - --- 2025-03-27 Atish Patra New
[v5,09/21] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing Add Counter delegation ISA extension support - - - - --- 2025-03-27 Atish Patra New
[v5,08/21] RISC-V: Add Sscfg extension CSR definition Add Counter delegation ISA extension support - - 1 - --- 2025-03-27 Atish Patra New
[v5,07/21] dt-bindings: riscv: add Smcntrpmf ISA extension description Add Counter delegation ISA extension support 1 - - - --- 2025-03-27 Atish Patra New
[v5,06/21] RISC-V: Add Smcntrpmf extension parsing Add Counter delegation ISA extension support - - 1 - --- 2025-03-27 Atish Patra New
[v5,05/21] RISC-V: Define indirect CSR access helpers Add Counter delegation ISA extension support - - - - --- 2025-03-27 Atish Patra New
[v5,04/21] dt-bindings: riscv: add Sxcsrind ISA extension description Add Counter delegation ISA extension support 1 - - - --- 2025-03-27 Atish Patra New
[v5,03/21] RISC-V: Add Sxcsrind ISA extension definition and parsing Add Counter delegation ISA extension support - - - - --- 2025-03-27 Atish Patra New
[v5,02/21] RISC-V: Add Sxcsrind ISA extension CSR definitions Add Counter delegation ISA extension support - - 1 - --- 2025-03-27 Atish Patra New
[v5,01/21] perf pmu-events: Add functions in jevent.py to parse counter and event info for hardware… Add Counter delegation ISA extension support - - - - --- 2025-03-27 Atish Patra New
[3/3] KVM: riscv: selftests: Add vector extension tests RISC-V KVM selftests improvements - - 1 - --- 2025-03-25 Atish Patra New
[2/3] KVM: riscv: selftests: Decode stval to identify exact exception type RISC-V KVM selftests improvements - - 1 - --- 2025-03-25 Atish Patra New
[1/3] KVM: riscv: selftests: Add stval to exception handling RISC-V KVM selftests improvements - - 1 - --- 2025-03-25 Atish Patra New
[v4,21/21] Sync empty-pmu-events.c with autogenerated one Add Counter delegation ISA extension support - - - - --- 2025-02-06 Atish Patra New
[v4,20/21] tools/perf: Pass the Counter constraint values in the pmu events Add Counter delegation ISA extension support - - - - --- 2025-02-06 Atish Patra New
[v4,19/21] tools/perf: Support event code for arch standard events Add Counter delegation ISA extension support - - - - --- 2025-02-06 Atish Patra New
[v4,18/21] RISC-V: perf: Add Qemu virt machine events Add Counter delegation ISA extension support - - - - --- 2025-02-06 Atish Patra New
[v4,17/21] RISC-V: perf: Add legacy event encodings via sysfs Add Counter delegation ISA extension support - - - - --- 2025-02-06 Atish Patra New
[v4,16/21] RISC-V: perf: Use config2/vendor table for event to counter mapping Add Counter delegation ISA extension support - - - - --- 2025-02-06 Atish Patra New
[v4,15/21] RISC-V: perf: Skip PMU SBI extension when not implemented Add Counter delegation ISA extension support - - - - --- 2025-02-06 Atish Patra New
[v4,14/21] RISC-V: perf: Implement supervisor counter delegation support Add Counter delegation ISA extension support - - - - --- 2025-02-06 Atish Patra New
[v4,13/21] RISC-V: perf: Add a mechanism to defined legacy event encoding Add Counter delegation ISA extension support - - - - --- 2025-02-06 Atish Patra New
[v4,12/21] RISC-V: perf: Modify the counter discovery mechanism Add Counter delegation ISA extension support - - - - --- 2025-02-06 Atish Patra New
[v4,11/21] RISC-V: perf: Restructure the SBI PMU code Add Counter delegation ISA extension support - - 1 - --- 2025-02-06 Atish Patra New
[v4,10/21] dt-bindings: riscv: add Counter delegation ISA extensions description Add Counter delegation ISA extension support - - - - --- 2025-02-06 Atish Patra New
[v4,09/21] RISC-V: Add Ssccfg ISA extension definition and parsing Add Counter delegation ISA extension support - - - - --- 2025-02-06 Atish Patra New
[v4,08/21] RISC-V: Add Sscfg extension CSR definition Add Counter delegation ISA extension support - - 1 - --- 2025-02-06 Atish Patra New
[v4,07/21] dt-bindings: riscv: add Smcntrpmf ISA extension description Add Counter delegation ISA extension support 1 - - - --- 2025-02-06 Atish Patra New
[v4,06/21] RISC-V: Add Smcntrpmf extension parsing Add Counter delegation ISA extension support - - 1 - --- 2025-02-06 Atish Patra New
[v4,05/21] RISC-V: Define indirect CSR access helpers Add Counter delegation ISA extension support - - - - --- 2025-02-06 Atish Patra New
[v4,04/21] dt-bindings: riscv: add Sxcsrind ISA extension description Add Counter delegation ISA extension support 1 - - - --- 2025-02-06 Atish Patra New
[v4,03/21] RISC-V: Add Sxcsrind ISA extension definition and parsing Add Counter delegation ISA extension support - - - - --- 2025-02-06 Atish Patra New
[v4,02/21] RISC-V: Add Sxcsrind ISA extension CSR definitions Add Counter delegation ISA extension support - - 1 - --- 2025-02-06 Atish Patra New
[v4,01/21] perf pmu-events: Add functions in jevent.py to parse counter and event info for hardware… Add Counter delegation ISA extension support - - - - --- 2025-02-06 Atish Patra New
[v2,9/9] RISC-V: KVM: Upgrade the supported SBI version to 3.0 Add SBI v3.0 PMU enhancements - - - - --- 2025-01-15 Atish Patra New
[v2,8/9] RISC-V: KVM: Implement get event info function Add SBI v3.0 PMU enhancements - - - - --- 2025-01-15 Atish Patra New
[v2,7/9] RISC-V: KVM: Use the new gpa range validate helper function Add SBI v3.0 PMU enhancements - - - - --- 2025-01-15 Atish Patra New
[v2,6/9] KVM: Add a helper function to validate vcpu gpa range Add SBI v3.0 PMU enhancements - - - - --- 2025-01-15 Atish Patra New
[v2,5/9] drivers/perf: riscv: Export PMU event info function Add SBI v3.0 PMU enhancements - - - - --- 2025-01-15 Atish Patra New
[v2,4/9] drivers/perf: riscv: Implement PMU event info function Add SBI v3.0 PMU enhancements - - - - --- 2025-01-15 Atish Patra New
[v2,3/9] RISC-V: KVM: Add support for Raw event v2 Add SBI v3.0 PMU enhancements - - - - --- 2025-01-15 Atish Patra New
[v2,2/9] drivers/perf: riscv: Add raw event v2 support Add SBI v3.0 PMU enhancements - - - - --- 2025-01-15 Atish Patra New
[v2,1/9] drivers/perf: riscv: Add SBI v3.0 flag Add SBI v3.0 PMU enhancements - - - - --- 2025-01-15 Atish Patra New