[v2,02/10] RISC-V: Add FIRMWARE_READ_HI definition

Message ID	20231229214950.4061381-3-atishp@rivosinc.com
State	Superseded
Headers	show Return-Path: <kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org> From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Conor Dooley <conor.dooley@microchip.com>, Anup Patel <anup@brainfault.org>, Albert Ou <aou@eecs.berkeley.edu>, Alexandre Ghiti <alexghiti@rivosinc.com>, Andrew Jones <ajones@ventanamicro.com>, Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>, Heiko Stuebner <heiko@sntech.de>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Will Deacon <will@kernel.org> Subject: [v2 02/10] RISC-V: Add FIRMWARE_READ_HI definition Date: Fri, 29 Dec 2023 13:49:42 -0800 Message-Id: <20231229214950.4061381-3-atishp@rivosinc.com> In-Reply-To: <20231229214950.4061381-1-atishp@rivosinc.com> References: <20231229214950.4061381-1-atishp@rivosinc.com> MIME-Version: 1.0 preview: SBI v2.0 added another function to SBI PMU extension to read the upper bits of a counter with width larger than XLEN. Add the definition for that function. Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/include/asm/sbi.h \| 1 + 1 file changed [...] Content analysis details: (0.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:336 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kvm-riscv" <kvm-riscv-bounces@lists.infradead.org> Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org
Series	RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest \| expand [v2,00/10] RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest [v2,01/10] RISC-V: Fix the typo in Scountovf CSR name [v2,02/10] RISC-V: Add FIRMWARE_READ_HI definition [v2,03/10] drivers/perf: riscv: Read upper bits of a firmware counter [v2,04/10] RISC-V: Add SBI PMU snapshot definitions [v2,05/10] drivers/perf: riscv: Implement SBI PMU snapshot function [v2,06/10] RISC-V: KVM: No need to update the counter value during reset [v2,07/10] RISC-V: KVM: No need to exit to the user space if perf event failed [v2,08/10] RISC-V: KVM: Implement SBI PMU Snapshot feature [v2,09/10] RISC-V: KVM: Add perf sampling support for guests [v2,10/10] RISC-V: KVM: Support 64 bit firmware counters on RV32

Message ID

20231229214950.4061381-3-atishp@rivosinc.com

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Superseded

Headers

From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Anup Patel <anup@brainfault.org>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alexghiti@rivosinc.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Atish Patra <atishp@atishpatra.org>,
	Guo Ren <guoren@kernel.org>,
	Heiko Stuebner <heiko@sntech.de>,
	kvm-riscv@lists.infradead.org,
	kvm@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Mark Rutland <mark.rutland@arm.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Will Deacon <will@kernel.org>
Subject: [v2 02/10] RISC-V: Add FIRMWARE_READ_HI definition
Date: Fri, 29 Dec 2023 13:49:42 -0800
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Series

RISC-V SBI v2.0 PMU improvements and Perf sampling in KVM guest | expand

Commit Message

Atish Kumar Patra Dec. 29, 2023, 9:49 p.m. UTC

SBI v2.0 added another function to SBI PMU extension to read
the upper bits of a counter with width larger than XLEN.

Add the definition for that function.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/include/asm/sbi.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index b6f898c56940..914eacc6ba2e 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -122,6 +122,7 @@  enum sbi_ext_pmu_fid {
 	SBI_EXT_PMU_COUNTER_START,
 	SBI_EXT_PMU_COUNTER_STOP,
 	SBI_EXT_PMU_COUNTER_FW_READ,
+	SBI_EXT_PMU_COUNTER_FW_READ_HI,
 };
 
 union sbi_pmu_ctr_info {

[v2,02/10] RISC-V: Add FIRMWARE_READ_HI definition

Commit Message

Patch