[RFC,29/48] RISC-V: KVM: Skip AIA CSR updates for TVMs

Message ID	20230419221716.3603068-30-atishp@rivosinc.com
State	Changes Requested
Headers	show Return-Path: <kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org> From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Alexandre Ghiti <alex@ghiti.fr>, Andrew Jones <ajones@ventanamicro.com>, Andrew Morton <akpm@linux-foundation.org>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= <bjorn@rivosinc.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>, Sean Christopherson <seanjc@google.com>, linux-coco@lists.linux.dev, Dylan Reid <dylan@rivosinc.com>, abrestic@rivosinc.com, Samuel Ortiz <sameo@rivosinc.com>, Christoph Hellwig <hch@infradead.org>, Conor Dooley <conor.dooley@microchip.com>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Guo Ren <guoren@kernel.org>, Heiko Stuebner <heiko@sntech.de>, Jiri Slaby <jirislaby@kernel.org>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, Mayuresh Chitale <mchitale@ventanamicro.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rajnesh Kanwal <rkanwal@rivosinc.com>, Uladzislau Rezki <urezki@gmail.com> Subject: [RFC 29/48] RISC-V: KVM: Skip AIA CSR updates for TVMs Date: Wed, 19 Apr 2023 15:16:57 -0700 Message-Id: <20230419221716.3603068-30-atishp@rivosinc.com> In-Reply-To: <20230419221716.3603068-1-atishp@rivosinc.com> References: <20230419221716.3603068-1-atishp@rivosinc.com> MIME-Version: 1.0 preview: For TVMs, the host must not support AIA CSR emulation. In addition to that, during vcpu load/put the CSR updates are not necessary as the CSR state must not be visible to the host. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- arch/riscv/kvm/aia.c \| 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) Content analysis details: (0.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:92e listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kvm-riscv" <kvm-riscv-bounces@lists.infradead.org> Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org
Series	RISC-V CoVE support \| expand [RFC,00/48] RISC-V CoVE support [RFC,01/48] mm/vmalloc: Introduce arch hooks to notify ioremap/unmap changes [RFC,02/48] RISC-V: KVM: Improve KVM error reporting to the user space [RFC,03/48] RISC-V: KVM: Invoke aia_update with preempt disabled/irq enabled [RFC,04/48] RISC-V: KVM: Add a helper function to get pgd size [RFC,05/48] RISC-V: Add COVH SBI extensions definitions [RFC,06/48] RISC-V: KVM: Implement COVH SBI extension [RFC,07/48] RISC-V: KVM: Add a barebone CoVE implementation [RFC,08/48] RISC-V: KVM: Add UABI to support static memory region attestation [RFC,09/48] RISC-V: KVM: Add CoVE related nacl helpers [RFC,10/48] RISC-V: KVM: Implement static memory region measurement [RFC,11/48] RISC-V: KVM: Use the new VM IOCTL for measuring pages [RFC,12/48] RISC-V: KVM: Exit to the user space for trap redirection [RFC,13/48] RISC-V: KVM: Return early for gstage modifications [RFC,14/48] RISC-V: KVM: Skip dirty logging updates for TVM [RFC,15/48] RISC-V: KVM: Add a helper function to trigger fence ops [RFC,16/48] RISC-V: KVM: Skip most VCPU requests for TVMs [RFC,17/48] RISC-V : KVM: Skip vmid/hgatp management for TVMs [RFC,18/48] RISC-V: KVM: Skip TLB management for TVMs [RFC,19/48] RISC-V: KVM: Register memory regions as confidential for TVMs [RFC,20/48] RISC-V: KVM: Add gstage mapping for TVMs [RFC,21/48] RISC-V: KVM: Handle SBI call forward from the TSM [RFC,22/48] RISC-V: KVM: Implement vcpu load/put functions for CoVE guests [RFC,23/48] RISC-V: KVM: Wireup TVM world switch [RFC,24/48] RISC-V: KVM: Update timer functionality for TVMs. [RFC,25/48] RISC-V: KVM: Skip HVIP update for TVMs [RFC,26/48] RISC-V: Add COVI extension definitions [RFC,27/48] RISC-V: KVM: Implement COVI SBI extension [RFC,28/48] RISC-V: KVM: Add interrupt management functions for TVM [RFC,29/48] RISC-V: KVM: Skip AIA CSR updates for TVMs [RFC,30/48] RISC-V: KVM: Perform limited operations in hardware enable/disable [RFC,31/48] RISC-V: KVM: Indicate no support user space emulated IRQCHIP [RFC,32/48] RISC-V: KVM: Add AIA support for TVMs [RFC,33/48] RISC-V: KVM: Hookup TVM VCPU init/destroy [RFC,34/48] RISC-V: KVM: Initialize CoVE [RFC,35/48] RISC-V: KVM: Add TVM init/destroy calls [RFC,36/48] RISC-V: KVM: Read/write gprs from/to shmem in case of TVM VCPU. [RFC,37/48] RISC-V: Add COVG SBI extension definitions [RFC,38/48] RISC-V: Add CoVE guest config and helper functions [RFC,39/48] RISC-V: Implement COVG SBI extension [RFC,40/48] RISC-V: COVE: Add COVH invalidate, validate, promote, demote and remove APIs. [RFC,41/48] RISC-V: KVM: Add host side support to handle COVG SBI calls. [RFC,42/48] RISC-V: Allow host to inject any ext interrupt id to a CoVE guest. [RFC,43/48] RISC-V: Add base memory encryption functions. [RFC,44/48] RISC-V: Add cc_platform_has() for RISC-V for CoVE [RFC,45/48] RISC-V: ioremap: Implement for arch specific ioremap hooks [RFC,46/48] riscv/virtio: Have CoVE guests enforce restricted virtio memory access. [RFC,47/48] RISC-V: Add shared bounce buffer to support DBCN for CoVE Guest. [RFC,48/48] drivers/hvc: sbi: Disable HVC console for TVMs

Message ID

20230419221716.3603068-30-atishp@rivosinc.com

State

Changes Requested

Headers

From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>, Alexandre Ghiti <alex@ghiti.fr>,
 Andrew Jones <ajones@ventanamicro.com>,
 Andrew Morton <akpm@linux-foundation.org>, Anup Patel <anup@brainfault.org>,
 Atish Patra <atishp@atishpatra.org>,
 =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= <bjorn@rivosinc.com>,
 Suzuki K Poulose <suzuki.poulose@arm.com>, Will Deacon <will@kernel.org>,
 Marc Zyngier <maz@kernel.org>, Sean Christopherson <seanjc@google.com>,
 linux-coco@lists.linux.dev, Dylan Reid <dylan@rivosinc.com>,
 abrestic@rivosinc.com, Samuel Ortiz <sameo@rivosinc.com>,
 Christoph Hellwig <hch@infradead.org>,
 Conor Dooley <conor.dooley@microchip.com>,
 Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Guo Ren <guoren@kernel.org>,
 Heiko Stuebner <heiko@sntech.de>, Jiri Slaby <jirislaby@kernel.org>,
 kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org,
 linux-riscv@lists.infradead.org,
 Mayuresh Chitale <mchitale@ventanamicro.com>,
 Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>,
 Paul Walmsley <paul.walmsley@sifive.com>,
 Rajnesh Kanwal <rkanwal@rivosinc.com>, Uladzislau Rezki <urezki@gmail.com>
Subject: [RFC 29/48] RISC-V: KVM: Skip AIA CSR updates for TVMs
Date: Wed, 19 Apr 2023 15:16:57 -0700
Message-Id: <20230419221716.3603068-30-atishp@rivosinc.com>
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Series

RISC-V CoVE support | expand

Commit Message

Atish Kumar Patra April 19, 2023, 10:16 p.m. UTC

For TVMs, the host must not support AIA CSR emulation. In addition to
that, during vcpu load/put the CSR updates are not necessary as the CSR
state must not be visible to the host.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/kvm/aia.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kvm/aia.c b/arch/riscv/kvm/aia.c
index 71216e1..e3da661 100644
--- a/arch/riscv/kvm/aia.c
+++ b/arch/riscv/kvm/aia.c
@@ -15,6 +15,7 @@ 
 #include <linux/percpu.h>
 #include <linux/spinlock.h>
 #include <asm/hwcap.h>
+#include <asm/kvm_cove.h>
 
 struct aia_hgei_control {
 	raw_spinlock_t lock;
@@ -134,7 +135,7 @@  void kvm_riscv_vcpu_aia_load(struct kvm_vcpu *vcpu, int cpu)
 {
 	struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr;
 
-	if (!kvm_riscv_aia_available())
+	if (!kvm_riscv_aia_available() || is_cove_vcpu(vcpu))
 		return;
 
 	csr_write(CSR_VSISELECT, csr->vsiselect);
@@ -152,7 +153,7 @@  void kvm_riscv_vcpu_aia_put(struct kvm_vcpu *vcpu)
 {
 	struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr;
 
-	if (!kvm_riscv_aia_available())
+	if (!kvm_riscv_aia_available() || is_cove_vcpu(vcpu))
 		return;
 
 	csr->vsiselect = csr_read(CSR_VSISELECT);
@@ -370,6 +371,10 @@  int kvm_riscv_vcpu_aia_rmw_ireg(struct kvm_vcpu *vcpu, unsigned int csr_num,
 	if (!kvm_riscv_aia_available())
 		return KVM_INSN_ILLEGAL_TRAP;
 
+	/* TVMs do not support AIA emulation */
+	if (is_cove_vcpu(vcpu))
+		return KVM_INSN_EXIT_TO_USER_SPACE;
+
 	/* First try to emulate in kernel space */
 	isel = csr_read(CSR_VSISELECT) & ISELECT_MASK;
 	if (isel >= ISELECT_IPRIO0 && isel <= ISELECT_IPRIO15)
@@ -529,6 +534,9 @@  void kvm_riscv_aia_enable(void)
 	if (!kvm_riscv_aia_available())
 		return;
 
+	if (unlikely(kvm_riscv_cove_enabled()))
+		goto enable_gext;
+
 	aia_set_hvictl(false);
 	csr_write(CSR_HVIPRIO1, 0x0);
 	csr_write(CSR_HVIPRIO2, 0x0);
@@ -539,6 +547,7 @@  void kvm_riscv_aia_enable(void)
 	csr_write(CSR_HVIPRIO2H, 0x0);
 #endif
 
+enable_gext:
 	/* Enable per-CPU SGEI interrupt */
 	enable_percpu_irq(hgei_parent_irq,
 			  irq_get_trigger_type(hgei_parent_irq));
@@ -559,7 +568,9 @@  void kvm_riscv_aia_disable(void)
 	csr_clear(CSR_HIE, BIT(IRQ_S_GEXT));
 	disable_percpu_irq(hgei_parent_irq);
 
-	aia_set_hvictl(false);
+	/* The host is not allowed modify hvictl for TVMs */
+	if (!unlikely(kvm_riscv_cove_enabled()))
+		aia_set_hvictl(false);
 
 	raw_spin_lock_irqsave(&hgctrl->lock, flags);

[RFC,29/48] RISC-V: KVM: Skip AIA CSR updates for TVMs

Commit Message

Patch