@@ -250,6 +250,31 @@ static bool pmu_sbi_ctr_is_fw(int cidx)
return (info->type == SBI_PMU_CTR_TYPE_FW) ? true : false;
}
+/*
+ * Returns the counter width of a programmable counter
+ * As we don't support heterneous CPUs yet, it is okay to just
+ * return the counter width of the first programmable counter.
+ */
+int riscv_pmu_sbi_hpmc_width(void)
+{
+ int i;
+ union sbi_pmu_ctr_info *info;
+
+ if (!rvpmu)
+ return -EINVAL;
+
+ for (i = 0; i < rvpmu->num_counters; i++) {
+ info = &pmu_ctr_list[i];
+ if (!info)
+ continue;
+ if (info->type == SBI_PMU_CTR_TYPE_HW)
+ return info->width;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(riscv_pmu_sbi_hpmc_width);
+
static int pmu_sbi_ctr_get_idx(struct perf_event *event)
{
struct hw_perf_event *hwc = &event->hw;
@@ -72,6 +72,7 @@ static inline void riscv_pmu_legacy_skip_init(void) {};
struct riscv_pmu *riscv_pmu_alloc(void);
#ifdef CONFIG_RISCV_PMU_SBI
int riscv_pmu_sbi_get_num_hw_ctrs(void);
+int riscv_pmu_sbi_hpmc_width(void);
#endif
#endif /* CONFIG_RISCV_PMU */
The virtual hardware counters need to have the same width as the logical hardware counters for simplicity. However, there shouldn't be mapping between virtual hardware counters and logical hardware counters. As we don't support hetergeneous harts or counters with different width as of now, the implementation relies on the counter width of the first available programmable counter. Signed-off-by: Atish Patra <atishp@rivosinc.com> --- drivers/perf/riscv_pmu_sbi.c | 25 +++++++++++++++++++++++++ include/linux/perf/riscv_pmu.h | 1 + 2 files changed, 26 insertions(+)