RISC-V: testsuite: Fix SELECT_VL SLP fallout.

Hi,

this fixes asm-scan fallout from r15-3712-g5e3a4a01785e2d where we allow
SLP with SELECT_VL.

Assisted by sed and regtested on rv64gcv_zvfh_zvbb.

Rather lengthy but obvious, so going to commit after a while if the CI is
happy.  I think those tests don't really need to check for vsetvl anyway,
not all of them at least but I didn't change that for now.

Regards
 Robin

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c: Expect
	length-controlled loop.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c:
	Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c:
	Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c:
	Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c: Ditto.
---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c  | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c  | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c  | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c       | 2 +-
 103 files changed, 103 insertions(+), 103 deletions(-)

On 9/19/24 7:24 AM, Robin Dapp wrote:
> Hi,
> 
> this fixes asm-scan fallout from r15-3712-g5e3a4a01785e2d where we allow
> SLP with SELECT_VL.
> 
> Assisted by sed and regtested on rv64gcv_zvfh_zvbb.
> 
> Rather lengthy but obvious, so going to commit after a while if the CI is
> happy.  I think those tests don't really need to check for vsetvl anyway,
> not all of them at least but I didn't change that for now.
Methodology works for me.
jeff

Thanks Robin.

> I think those tests don't really need to check for vsetvl anyway.
Looks only scan asm for RVV fixed-pointer insn is good enough for vector part, which
is somehow different to scalar. I will make the change after this patch pushed.

Pan

-----Original Message-----
From: Robin Dapp <rdapp.gcc@gmail.com> 
Sent: Thursday, September 19, 2024 9:25 PM
To: gcc-patches <gcc-patches@gcc.gnu.org>
Cc: palmer@dabbelt.com; kito.cheng@gmail.com; juzhe.zhong@rivai.ai; jeffreyalaw@gmail.com; Li, Pan2 <pan2.li@intel.com>; rdapp.gcc@gmail.com
Subject: [PATCH] RISC-V: testsuite: Fix SELECT_VL SLP fallout.

Hi,

this fixes asm-scan fallout from r15-3712-g5e3a4a01785e2d where we allow
SLP with SELECT_VL.

Assisted by sed and regtested on rv64gcv_zvfh_zvbb.

Rather lengthy but obvious, so going to commit after a while if the CI is
happy.  I think those tests don't really need to check for vsetvl anyway,
not all of them at least but I didn't change that for now.

Regards
 Robin

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c: Expect
	length-controlled loop.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c:
	Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c:
	Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c:
	Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c: Ditto.
---
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c        | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c  | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c  | 2 +-
 .../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c  | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c      | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c       | 2 +-
 .../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c       | 2 +-
 103 files changed, 103 insertions(+), 103 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c
index 8677353a0b6..bb295f0b794 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_s_add_int8_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c
index 4c6ec43f909..3af0b6640ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_s_add_int16_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c
index 6e44eb3b6c8..2371d77b696 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_s_add_int32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c
index bbf84861bca..9aec29f6e38 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_s_add_int64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c
index d7d1dae010d..e65631c1ed8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c
index 4397c10943a..d67ac34e3ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c
index b93b582680f..db0b0f3415f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c
index ec3c6af4ee6..faf23ee918f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
index 35f17c1b82d..ae57bb24678 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c
index 11690843160..fd4820b415c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
index 9949047a6c7..efa4af38a51 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c
index 84c44f9a46b..80b2a38b06a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c
index 5f61acbec0d..2cd9dec6232 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c
index eb4486ca765..7836d0d72f8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c
index 470eb6b3cfe..137f79f0b55 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
index b381c05091a..d853cec7935 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c
index 6bd2c30c139..74d585560a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
index 47dd5012cc6..8c32916f622 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
index df8d5a8d275..3c41500bf06 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
index f286bd10e4b..00dc2babe46 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c
index 307ff36cc35..43049fd86cb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
index 3218962724c..bcb01f02f20 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c
index 922df02278d..d4304d58511 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c
index 7653f81531c..923b658a613 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c
index 18803afd19a..20d0d1ba95e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
index e95d6f73c38..bff69557438 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c
index 97a9b1fb973..afc8e5dbadb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c
index 34e10236381..874d26d8887 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c
index 7fc5e73fe1d..fe7ed2647da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c
index 9684fdf37f7..a00412e81dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c
index 8da2cb413d8..f680a31158d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
index 96787fc15e2..64fc4092e83 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
index f155d7c47c7..a4eae4c7a00 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c
index 5fdb67cc1ca..d000e8c5810 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c
index eee4d902fb5..d25820fd897 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c
index d636302842c..42723a07a76 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
index 5d214301727..bd8fbc192b4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
index e50121bd031..52c2a686881 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
index de460c176a2..37fde86fe31 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
index 96e06f0c6be..c6f33cff650 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
index dffe957629a..426220969d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
index 97b2e17e74a..9d16b838195 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
index 978c37ca138..f673839f0e7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
index f43c5711eca..cd9af177e94 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
index f435b6e0831..f74f0750932 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
index 74fe1e31804..0f8f909c525 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
index b83b87b2b1b..9b627e6a342 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
index 549970684fa..d2d0c04935b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
index 0ae3c37a783..cab29386257 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
index e16a0d22cbb..78261081fe3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
index 6b4bc69c005..04a2c58e242 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
index 6be7c7669de..eb7dac69989 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
index e9eb157fb9d..6a1551122a9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
index 4980789dcd4..4611ac7b09b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
index 2a4d1cc93e7..ee0853d6f71 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
index 8c14d9a2c01..7af569d9219 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
index 32d3a62d303..70ae9298356 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
index 8c098ac336a..1ff020ff878 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
index 2af04851e04..3dde5f27f4d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
index 4a4fc746326..b658c226199 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
index 5c912a32549..df1435dbb3e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
index 50aa0ae59d7..77e33234575 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
index 329dd230b02..4885dda08ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_9:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
index a024eadc2a7..33d69e193a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_9:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
index 56216e97620..a050e0df8c3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_9:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
index 707bfd2e1c6..0abb6e0a86c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_9:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
index e7dc212fe52..f40f56da9d9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_10:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
index b814830da32..7031f16bf5e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_10:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
index e6c6aaac800..0cc1298fa9a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_10:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
index 21727fb3a43..00a671983f7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
index 716e58e8ae3..2aba688eb97 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_10:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
index e1d78aff28c..86cd920bd0c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
index 9911cbcfb37..d8880e55f95 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
index 8c83af1fc67..6ba1d1bb12a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
index d76d754b721..b3e40ed31b3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
index 3b6b53274f2..ffc68e7b6dc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
index 792d8a02877..1386f52d020 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_trunc_uint8_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
index 67780360ce1..959e2e1a293 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_trunc_uint16_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
index 04f2d0b2d95..769e0af309e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_sub_trunc_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
 ** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
index 60ab5382fa9..186005733ec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
index 2566450445f..6ee407dd04c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
index f90432bb903..bd3e108bd52 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
index 5330e19c679..4821e13d0c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
index 45d74eab2cd..d83ce7f6b03 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
index c9ce8788274..2098e8b17c3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c
index 5529c710f92..1ffd507eece 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c
index 6d773e96da3..99c6cedf82f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c
index 808f62bff10..8dd648854ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c
index 12a0e2ff380..f3ab601a753 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
index 9c7979d326c..f0104c7918a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c
index cf6f404f65e..f65b747ca11 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
index 2e497b7ec1c..0c8988dd0d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c
index dd996d21c5e..01fb666273b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c
index a6c125408ce..0d899b7d329 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c
index 2551b2f5a05..1a26484da8a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c
index bfcfa805e19..344f72049e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c
index 787c5644bb0..6bdab50242c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c
index b236c2a2caf..4b1998c635f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c
index 1747585c59e..048c3abd17c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c
index fd30184b1de..79fdbb6937c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c
index dc9bbb5fe96..0d96c477a88 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c
index 0525b8f5159..0eb3aedeba9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c
index 96621231999..97bcb182e2c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c
@@ -8,7 +8,7 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
 ** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
 ** ...