diff mbox series

[2/4] Match: Support form 3 for vector signed integer SAT_SUB

Message ID 20241012042605.3788448-2-pan2.li@intel.com
State New
Headers show
Series [1/4] RISC-V: Add testcases for form 2 of vector signed SAT_SUB | expand

Commit Message

Li, Pan2 Oct. 12, 2024, 4:26 a.m. UTC 
From: Pan Li <pan2.li@intel.com>

This patch would like to support the form 3 of the vector signed
integer SAT_SUB.  Aka below example:

Form 3:
  #define DEF_VEC_SAT_S_SUB_FMT_3(T, UT, MIN, MAX)                     \
  void __attribute__((noinline))                                       \
  vec_sat_s_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        T minus;                                                       \
        bool overflow = __builtin_sub_overflow (x, y, &minus);         \
        out[i] = overflow ? x < 0 ? MIN : MAX : minus;                 \
      }                                                                \
  }

Before this patch:
  25   │   if (limit_11(D) != 0)
  26   │     goto <bb 3>; [89.00%]
  27   │   else
  28   │     goto <bb 8>; [11.00%]
  29   │ ;;    succ:       3
  30   │ ;;                8
  31   │
  32   │ ;;   basic block 3, loop depth 0
  33   │ ;;    pred:       2
  34   │   _13 = (unsigned long) limit_11(D);
  35   │ ;;    succ:       4
  36   │
  37   │ ;;   basic block 4, loop depth 1
  38   │ ;;    pred:       3
  39   │ ;;                7
  40   │   # ivtmp.7_34 = PHI <0(3), ivtmp.7_30(7)>
  41   │   _26 = op_1_12(D) + ivtmp.7_34;
  42   │   x_29 = MEM[(int8_t *)_26];
  43   │   _1 = op_2_14(D) + ivtmp.7_34;
  44   │   y_24 = MEM[(int8_t *)_1];
  45   │   _9 = .SUB_OVERFLOW (x_29, y_24);
  46   │   _7 = IMAGPART_EXPR <_9>;
  47   │   if (_7 != 0)
  48   │     goto <bb 6>; [50.00%]
  49   │   else
  50   │     goto <bb 5>; [50.00%]
  51   │ ;;    succ:       6
  52   │ ;;                5
  53   │
  54   │ ;;   basic block 5, loop depth 1
  55   │ ;;    pred:       4
  56   │   _42 = REALPART_EXPR <_9>;
  57   │   _2 = out_17(D) + ivtmp.7_34;
  58   │   MEM[(int8_t *)_2] = _42;
  59   │   ivtmp.7_27 = ivtmp.7_34 + 1;
  60   │   if (_13 != ivtmp.7_27)
  61   │     goto <bb 7>; [89.00%]
  62   │   else
  63   │     goto <bb 8>; [11.00%]
  64   │ ;;    succ:       7
  65   │ ;;                8
  66   │
  67   │ ;;   basic block 6, loop depth 1
  68   │ ;;    pred:       4
  69   │   _38 = x_29 < 0;
  70   │   _39 = (signed char) _38;
  71   │   _40 = -_39;
  72   │   _41 = _40 ^ 127;
  73   │   _33 = out_17(D) + ivtmp.7_34;
  74   │   MEM[(int8_t *)_33] = _41;
  75   │   ivtmp.7_25 = ivtmp.7_34 + 1;
  76   │   if (_13 != ivtmp.7_25)
  77   │     goto <bb 7>; [89.00%]
  78   │   else
  79   │     goto <bb 8>; [11.00%]

After this patch:
  77   │   _94 = .SELECT_VL (ivtmp_92, POLY_INT_CST [16, 16]);
  78   │   vect_x_13.9_81 = .MASK_LEN_LOAD (vectp_op_1.7_79, 8B, { -1, ... }, _94, 0);
  79   │   vect_y_15.12_85 = .MASK_LEN_LOAD (vectp_op_2.10_83, 8B, { -1, ... }, _94, 0);
  80   │   vect_patt_49.13_86 = .SAT_SUB (vect_x_13.9_81, vect_y_15.12_85);
  81   │   .MASK_LEN_STORE (vectp_out.14_88, 8B, { -1, ... }, _94, 0, vect_patt_49.13_86);
  82   │   vectp_op_1.7_80 = vectp_op_1.7_79 + _94;
  83   │   vectp_op_2.10_84 = vectp_op_2.10_83 + _94;
  84   │   vectp_out.14_89 = vectp_out.14_88 + _94;
  85   │   ivtmp_93 = ivtmp_92 - _94;

The below test suites are passed for this patch.
* The rv64gcv fully regression test.
* The x86 bootstrap test.
* The x86 fully regression test.

gcc/ChangeLog:

	* match.pd: Add matching pattern for vector signed SAT_SUB form 3.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/match.pd | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Richard Biener Oct. 12, 2024, 12:10 p.m. UTC | #1 
On Sat, Oct 12, 2024 at 6:27 AM <pan2.li@intel.com> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to support the form 3 of the vector signed
> integer SAT_SUB.  Aka below example:
>
> Form 3:
>   #define DEF_VEC_SAT_S_SUB_FMT_3(T, UT, MIN, MAX)                     \
>   void __attribute__((noinline))                                       \
>   vec_sat_s_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
>   {                                                                    \
>     unsigned i;                                                        \
>     for (i = 0; i < limit; i++)                                        \
>       {                                                                \
>         T x = op_1[i];                                                 \
>         T y = op_2[i];                                                 \
>         T minus;                                                       \
>         bool overflow = __builtin_sub_overflow (x, y, &minus);         \
>         out[i] = overflow ? x < 0 ? MIN : MAX : minus;                 \
>       }                                                                \
>   }
>
> Before this patch:
>   25   │   if (limit_11(D) != 0)
>   26   │     goto <bb 3>; [89.00%]
>   27   │   else
>   28   │     goto <bb 8>; [11.00%]
>   29   │ ;;    succ:       3
>   30   │ ;;                8
>   31   │
>   32   │ ;;   basic block 3, loop depth 0
>   33   │ ;;    pred:       2
>   34   │   _13 = (unsigned long) limit_11(D);
>   35   │ ;;    succ:       4
>   36   │
>   37   │ ;;   basic block 4, loop depth 1
>   38   │ ;;    pred:       3
>   39   │ ;;                7
>   40   │   # ivtmp.7_34 = PHI <0(3), ivtmp.7_30(7)>
>   41   │   _26 = op_1_12(D) + ivtmp.7_34;
>   42   │   x_29 = MEM[(int8_t *)_26];
>   43   │   _1 = op_2_14(D) + ivtmp.7_34;
>   44   │   y_24 = MEM[(int8_t *)_1];
>   45   │   _9 = .SUB_OVERFLOW (x_29, y_24);
>   46   │   _7 = IMAGPART_EXPR <_9>;
>   47   │   if (_7 != 0)
>   48   │     goto <bb 6>; [50.00%]
>   49   │   else
>   50   │     goto <bb 5>; [50.00%]
>   51   │ ;;    succ:       6
>   52   │ ;;                5
>   53   │
>   54   │ ;;   basic block 5, loop depth 1
>   55   │ ;;    pred:       4
>   56   │   _42 = REALPART_EXPR <_9>;
>   57   │   _2 = out_17(D) + ivtmp.7_34;
>   58   │   MEM[(int8_t *)_2] = _42;
>   59   │   ivtmp.7_27 = ivtmp.7_34 + 1;
>   60   │   if (_13 != ivtmp.7_27)
>   61   │     goto <bb 7>; [89.00%]
>   62   │   else
>   63   │     goto <bb 8>; [11.00%]
>   64   │ ;;    succ:       7
>   65   │ ;;                8
>   66   │
>   67   │ ;;   basic block 6, loop depth 1
>   68   │ ;;    pred:       4
>   69   │   _38 = x_29 < 0;
>   70   │   _39 = (signed char) _38;
>   71   │   _40 = -_39;
>   72   │   _41 = _40 ^ 127;
>   73   │   _33 = out_17(D) + ivtmp.7_34;
>   74   │   MEM[(int8_t *)_33] = _41;
>   75   │   ivtmp.7_25 = ivtmp.7_34 + 1;
>   76   │   if (_13 != ivtmp.7_25)
>   77   │     goto <bb 7>; [89.00%]
>   78   │   else
>   79   │     goto <bb 8>; [11.00%]
>
> After this patch:
>   77   │   _94 = .SELECT_VL (ivtmp_92, POLY_INT_CST [16, 16]);
>   78   │   vect_x_13.9_81 = .MASK_LEN_LOAD (vectp_op_1.7_79, 8B, { -1, ... }, _94, 0);
>   79   │   vect_y_15.12_85 = .MASK_LEN_LOAD (vectp_op_2.10_83, 8B, { -1, ... }, _94, 0);
>   80   │   vect_patt_49.13_86 = .SAT_SUB (vect_x_13.9_81, vect_y_15.12_85);
>   81   │   .MASK_LEN_STORE (vectp_out.14_88, 8B, { -1, ... }, _94, 0, vect_patt_49.13_86);
>   82   │   vectp_op_1.7_80 = vectp_op_1.7_79 + _94;
>   83   │   vectp_op_2.10_84 = vectp_op_2.10_83 + _94;
>   84   │   vectp_out.14_89 = vectp_out.14_88 + _94;
>   85   │   ivtmp_93 = ivtmp_92 - _94;
>
> The below test suites are passed for this patch.
> * The rv64gcv fully regression test.
> * The x86 bootstrap test.
> * The x86 fully regression test.

OK.

Thanks,
Richard.

> gcc/ChangeLog:
>
>         * match.pd: Add matching pattern for vector signed SAT_SUB form 3.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
>  gcc/match.pd | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/gcc/match.pd b/gcc/match.pd
> index f2b5f3af9ef..2ab76f9d055 100644
> --- a/gcc/match.pd
> +++ b/gcc/match.pd
> @@ -3417,6 +3417,18 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
>         @2)
>   (if (INTEGRAL_TYPE_P (type) && !TYPE_UNSIGNED (type))))
>
> +/* Signed saturation sub, case 5:
> +   Z = .SUB_OVERFLOW (X, Y)
> +   SAT_S_SUB = IMAGPART_EXPR (Z) != 0 ? (-(T)(X < 0) ^ MAX) : minus;  */
> +(match (signed_integer_sat_sub @0 @1)
> + (cond^ (ne (imagpart (IFN_SUB_OVERFLOW:c@2 @0 @1)) integer_zerop)
> +       (bit_xor:c (nop_convert?
> +                   (negate (nop_convert? (convert (lt @0 integer_zerop)))))
> +                  max_value)
> +       (realpart @2))
> + (if (INTEGRAL_TYPE_P (type) && !TYPE_UNSIGNED (type)
> +      && types_match (type, @0, @1))))
> +
>  /* Unsigned saturation truncate, case 1, sizeof (WT) > sizeof (NT).
>     SAT_U_TRUNC = (NT)x | (NT)(-(X > (WT)(NT)(-1))).  */
>  (match (unsigned_integer_sat_trunc @0)
> --
> 2.43.0
>
Jakub Jelinek Oct. 14, 2024, 12:05 p.m. UTC | #2 
On Sat, Oct 12, 2024 at 02:10:49PM +0200, Richard Biener wrote:
> > gcc/ChangeLog:
> >
> >         * match.pd: Add matching pattern for vector signed SAT_SUB form 3.

I now see
../../gcc/match.pd:3424:3 warning: duplicate pattern
 (cond^ (ne (imagpart (IFN_SUB_OVERFLOW:c@2 @0 @1)) integer_zerop)
  ^
../../gcc/match.pd:3397:3 warning: previous pattern defined here
 (cond^ (ne (imagpart (IFN_SUB_OVERFLOW@2 @0 @1)) integer_zerop)
  ^
(similar message on those 2 lines 5 more times).

That doesn't look correct.

	Jakub
Li, Pan2 Oct. 14, 2024, 12:29 p.m. UTC | #3 
Thanks Jakub for reminder, let me eliminate the dup pattern.

Pan

-----Original Message-----
From: Jakub Jelinek <jakub@redhat.com> 
Sent: Monday, October 14, 2024 8:05 PM
To: Richard Biener <richard.guenther@gmail.com>
Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org; Tamar.Christina@arm.com; juzhe.zhong@rivai.ai; kito.cheng@gmail.com; jeffreyalaw@gmail.com; rdapp.gcc@gmail.com
Subject: Re: [PATCH 2/4] Match: Support form 3 for vector signed integer SAT_SUB

On Sat, Oct 12, 2024 at 02:10:49PM +0200, Richard Biener wrote:
> > gcc/ChangeLog:
> >
> >         * match.pd: Add matching pattern for vector signed SAT_SUB form 3.

I now see
../../gcc/match.pd:3424:3 warning: duplicate pattern
 (cond^ (ne (imagpart (IFN_SUB_OVERFLOW:c@2 @0 @1)) integer_zerop)
  ^
../../gcc/match.pd:3397:3 warning: previous pattern defined here
 (cond^ (ne (imagpart (IFN_SUB_OVERFLOW@2 @0 @1)) integer_zerop)
  ^
(similar message on those 2 lines 5 more times).

That doesn't look correct.

	Jakub
diff mbox series

Patch

diff --git a/gcc/match.pd b/gcc/match.pd
index f2b5f3af9ef..2ab76f9d055 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -3417,6 +3417,18 @@  DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
 	@2)
  (if (INTEGRAL_TYPE_P (type) && !TYPE_UNSIGNED (type))))
 
+/* Signed saturation sub, case 5:
+   Z = .SUB_OVERFLOW (X, Y)
+   SAT_S_SUB = IMAGPART_EXPR (Z) != 0 ? (-(T)(X < 0) ^ MAX) : minus;  */
+(match (signed_integer_sat_sub @0 @1)
+ (cond^ (ne (imagpart (IFN_SUB_OVERFLOW:c@2 @0 @1)) integer_zerop)
+	(bit_xor:c (nop_convert?
+		    (negate (nop_convert? (convert (lt @0 integer_zerop)))))
+		   max_value)
+	(realpart @2))
+ (if (INTEGRAL_TYPE_P (type) && !TYPE_UNSIGNED (type)
+      && types_match (type, @0, @1))))
+
 /* Unsigned saturation truncate, case 1, sizeof (WT) > sizeof (NT).
    SAT_U_TRUNC = (NT)x | (NT)(-(X > (WT)(NT)(-1))).  */
 (match (unsigned_integer_sat_trunc @0)