| Message ID | 20240925064559.2456520-1-pan2.li@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v1,1/3] RISC-V: Refine the testcase of vector SAT_ADD | expand |
LGTM juzhe.zhong@rivai.ai From: pan2.li Date: 2024-09-25 14:45 To: gcc-patches CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li Subject: [PATCH v1 3/3] RISC-V: Refine the testcase of vector SAT_TRUNC From: Pan Li <pan2.li@intel.com> Take scan-assembler-times for vsadd insn check instead of function body, as we only care about if we can generate the fixed point insn vnclip. The below test are passed for this patch. * The rv64gcv fully regression test. It is test only patch and obvious up to a point, will commit it directly if no comments in next 48H. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Remove func body check and take scan asm times instead. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com> --- .../rvv/autovec/unop/vec_sat_u_trunc-1.c | 13 ++---------- .../rvv/autovec/unop/vec_sat_u_trunc-10.c | 13 ++---------- .../rvv/autovec/unop/vec_sat_u_trunc-11.c | 16 +------------- .../rvv/autovec/unop/vec_sat_u_trunc-12.c | 12 +---------- .../rvv/autovec/unop/vec_sat_u_trunc-13.c | 13 ++---------- .../rvv/autovec/unop/vec_sat_u_trunc-14.c | 17 ++------------- .../rvv/autovec/unop/vec_sat_u_trunc-15.c | 21 ++----------------- .../rvv/autovec/unop/vec_sat_u_trunc-16.c | 13 ++---------- .../rvv/autovec/unop/vec_sat_u_trunc-17.c | 17 ++------------- .../rvv/autovec/unop/vec_sat_u_trunc-18.c | 13 ++---------- .../rvv/autovec/unop/vec_sat_u_trunc-19.c | 13 ++---------- .../rvv/autovec/unop/vec_sat_u_trunc-2.c | 17 ++------------- .../rvv/autovec/unop/vec_sat_u_trunc-20.c | 17 ++------------- .../rvv/autovec/unop/vec_sat_u_trunc-21.c | 21 ++----------------- .../rvv/autovec/unop/vec_sat_u_trunc-22.c | 13 ++---------- .../rvv/autovec/unop/vec_sat_u_trunc-23.c | 17 ++------------- .../rvv/autovec/unop/vec_sat_u_trunc-24.c | 13 ++---------- .../rvv/autovec/unop/vec_sat_u_trunc-3.c | 21 ++----------------- .../rvv/autovec/unop/vec_sat_u_trunc-4.c | 13 ++---------- .../rvv/autovec/unop/vec_sat_u_trunc-5.c | 17 ++------------- .../rvv/autovec/unop/vec_sat_u_trunc-6.c | 13 ++---------- .../rvv/autovec/unop/vec_sat_u_trunc-7.c | 13 ++---------- .../rvv/autovec/unop/vec_sat_u_trunc-8.c | 17 ++------------- .../rvv/autovec/unop/vec_sat_u_trunc-9.c | 21 ++----------------- 24 files changed, 46 insertions(+), 328 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c index 186005733ec..3d29d26abff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint16_t_fmt_1: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint16_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c index 6ee407dd04c..c9634d383ae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint16_t_uint32_t_fmt_2: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint32_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c index bd3e108bd52..17e176b87db 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c @@ -1,22 +1,8 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint16_t_uint64_t_fmt_2: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c index 4821e13d0c1..1ebf5c88d3a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c @@ -1,18 +1,8 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint32_t_uint64_t_fmt_2: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint32_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c index d83ce7f6b03..04d12048bc2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint16_t_fmt_3: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint16_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c index 2098e8b17c3..072d189224f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint32_t_fmt_3: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint32_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c index 1ffd507eece..837551ca6b6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint64_t_fmt_3: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c index 99c6cedf82f..3174f45fd60 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint16_t_uint32_t_fmt_3: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint32_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c index 8dd648854ef..f177f7bedd7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint16_t_uint64_t_fmt_3: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c index f3ab601a753..32a30f3692a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint32_t_uint64_t_fmt_3: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint32_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c index f0104c7918a..dd14fad454c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint16_t_fmt_4: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint16_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c index f65b747ca11..5354717cc46 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint32_t_fmt_1: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint32_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c index 0c8988dd0d8..b77fcd4a5bc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint32_t_fmt_4: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint32_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c index 01fb666273b..db788e19092 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint64_t_fmt_4: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c index 0d899b7d329..8b27b69cf08 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint16_t_uint32_t_fmt_4: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint32_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c index 1a26484da8a..df1752c05db 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint16_t_uint64_t_fmt_4: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c index 344f72049e0..200c559f855 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint32_t_uint64_t_fmt_4: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint32_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c index 6bdab50242c..15654b4bf8b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint64_t_fmt_1: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c index 4b1998c635f..1e272aeb726 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint16_t_uint32_t_fmt_1: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint32_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c index 048c3abd17c..eb7d96197bb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint16_t_uint64_t_fmt_1: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c index 79fdbb6937c..fc43a8a58f8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint32_t_uint64_t_fmt_1: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint32_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c index 0d96c477a88..b5a3fc3222d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint16_t_fmt_2: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint16_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c index 0eb3aedeba9..9ed21e21e33 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint32_t_fmt_2: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint32_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c index 97bcb182e2c..d93453f6890 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint64_t_fmt_2: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c index 186005733ec..3d29d26abff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint16_t_fmt_1: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint16_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c index 6ee407dd04c..c9634d383ae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint16_t_uint32_t_fmt_2: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint32_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c index bd3e108bd52..17e176b87db 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c @@ -1,22 +1,8 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint16_t_uint64_t_fmt_2: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c index 4821e13d0c1..1ebf5c88d3a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c @@ -1,18 +1,8 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint32_t_uint64_t_fmt_2: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint32_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c index d83ce7f6b03..04d12048bc2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint16_t_fmt_3: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint16_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c index 2098e8b17c3..072d189224f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint32_t_fmt_3: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint32_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c index 1ffd507eece..837551ca6b6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint64_t_fmt_3: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c index 99c6cedf82f..3174f45fd60 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint16_t_uint32_t_fmt_3: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint32_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c index 8dd648854ef..f177f7bedd7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint16_t_uint64_t_fmt_3: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c index f3ab601a753..32a30f3692a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint32_t_uint64_t_fmt_3: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_3 (uint32_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c index f0104c7918a..dd14fad454c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint16_t_fmt_4: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint16_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c index f65b747ca11..5354717cc46 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint32_t_fmt_1: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint32_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c index 0c8988dd0d8..b77fcd4a5bc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint32_t_fmt_4: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint32_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c index 01fb666273b..db788e19092 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint64_t_fmt_4: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c index 0d899b7d329..8b27b69cf08 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint16_t_uint32_t_fmt_4: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint32_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c index 1a26484da8a..df1752c05db 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint16_t_uint64_t_fmt_4: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c index 344f72049e0..200c559f855 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint32_t_uint64_t_fmt_4: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_4 (uint32_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c index 6bdab50242c..15654b4bf8b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint64_t_fmt_1: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 3 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c index 4b1998c635f..1e272aeb726 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint16_t_uint32_t_fmt_1: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint32_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c index 048c3abd17c..eb7d96197bb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint16_t_uint64_t_fmt_1: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c index 79fdbb6937c..fc43a8a58f8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint32_t_uint64_t_fmt_1: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_1 (uint32_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c index 0d96c477a88..b5a3fc3222d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint16_t_fmt_2: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint16_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c index 0eb3aedeba9..9ed21e21e33 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint32_t_fmt_2: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint32_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c index 97bcb182e2c..d93453f6890 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-skip-if "" { *-*-* } { "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */ #include "../vec_sat_arith.h" -/* -** vec_sat_u_trunc_uint8_t_uint64_t_fmt_2: -** ... -** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma -** ... -** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0 -** ... -*/ DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint64_t) /* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 4 "expand" } } */ +/* { dg-final { scan-assembler-times {vnclipu\.wi} 3 } } */