[v1,1/3] RISC-V: Refine the testcase of vector SAT_ADD

From: Pan Li <pan2.li@intel.com>

Take scan-assembler-times for vsadd insn check instead of function body,
as we only care about if we can generate the fixed point insn vsadd.

The below test are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c: Remove
	func body check and take scan asm times instead.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 .../riscv/rvv/autovec/binop/vec_sat_s_add-1.c       | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-2.c       | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-3.c       | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_s_add-4.c       | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-1.c       | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-10.c      |  5 ++---
 .../riscv/rvv/autovec/binop/vec_sat_u_add-11.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-12.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-13.c      | 12 +-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-14.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-15.c      | 12 +-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-16.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-17.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-18.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-19.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-2.c       | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-20.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-21.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-22.c      | 12 +-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-23.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-24.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-25.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-26.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-27.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-28.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-29.c      | 12 +-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-3.c       | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-30.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-31.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-32.c      | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-4.c       | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-5.c       | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-6.c       | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-7.c       | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-8.c       | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add-9.c       | 13 ++-----------
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c   | 13 ++++---------
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c  | 13 ++++---------
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c  | 13 ++++---------
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c  | 13 ++++---------
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c  | 13 ++++---------
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c  | 13 ++++---------
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c  | 12 +++---------
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c  | 13 ++++---------
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c   | 13 ++++---------
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c   | 13 ++++---------
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c   | 13 ++++---------
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c   | 13 ++++---------
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c   | 13 ++++---------
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c   | 12 +++---------
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c   | 13 ++++---------
 .../riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c   | 13 ++++---------
 52 files changed, 130 insertions(+), 532 deletions(-)

LGTM



juzhe.zhong@rivai.ai
 
From: pan2.li
Date: 2024-09-25 14:45
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 1/3] RISC-V: Refine the testcase of vector SAT_ADD
From: Pan Li <pan2.li@intel.com>
 
Take scan-assembler-times for vsadd insn check instead of function body,
as we only care about if we can generate the fixed point insn vsadd.
 
The below test are passed for this patch.
* The rv64gcv fully regression test.
 
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c: Remove
func body check and take scan asm times instead.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c: Ditto.
 
Signed-off-by: Pan Li <pan2.li@intel.com>
---
.../riscv/rvv/autovec/binop/vec_sat_s_add-1.c       | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_s_add-2.c       | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_s_add-3.c       | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_s_add-4.c       | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-1.c       | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-10.c      |  5 ++---
.../riscv/rvv/autovec/binop/vec_sat_u_add-11.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-12.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-13.c      | 12 +-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-14.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-15.c      | 12 +-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-16.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-17.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-18.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-19.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-2.c       | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-20.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-21.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-22.c      | 12 +-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-23.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-24.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-25.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-26.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-27.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-28.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-29.c      | 12 +-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-3.c       | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-30.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-31.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-32.c      | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-4.c       | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-5.c       | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-6.c       | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-7.c       | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-8.c       | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add-9.c       | 13 ++-----------
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c   | 13 ++++---------
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c  | 13 ++++---------
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c  | 13 ++++---------
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c  | 13 ++++---------
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c  | 13 ++++---------
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c  | 13 ++++---------
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c  | 12 +++---------
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c  | 13 ++++---------
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c   | 13 ++++---------
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c   | 13 ++++---------
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c   | 13 ++++---------
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c   | 13 ++++---------
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c   | 13 ++++---------
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c   | 12 +++---------
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c   | 13 ++++---------
.../riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c   | 13 ++++---------
52 files changed, 130 insertions(+), 532 deletions(-)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c
index bb295f0b794..60bb9ea0576 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-1.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_s_add_int8_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_S_ADD_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c
index 3af0b6640ef..c10521c15eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-2.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_s_add_int16_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_S_ADD_FMT_1(int16_t, uint16_t, INT16_MIN, INT16_MAX)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c
index 2371d77b696..b818878a7ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-3.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_s_add_int32_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_S_ADD_FMT_1(int32_t, uint32_t, INT32_MIN, INT32_MAX)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c
index 9aec29f6e38..8dbc7e81fbf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-4.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_s_add_int64_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_S_ADD_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c
index e65631c1ed8..4df3407eec2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint8_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_1(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c
index d67ac34e3ce..d31325a00ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c
@@ -1,7 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
@@ -16,3 +14,4 @@
DEF_VEC_SAT_U_ADD_FMT_3(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c
index db0b0f3415f..9c84b0f3292 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint32_t_fmt_3:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_3(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c
index faf23ee918f..4e87e0e6e73 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint64_t_fmt_3:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_3(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
index ae57bb24678..236fe68123f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
@@ -1,18 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint8_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_4(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c
index fd4820b415c..0092492a535 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint16_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_4(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
index efa4af38a51..2eda4197abb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
@@ -1,18 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint32_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_4(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c
index 80b2a38b06a..f1ee836cb9e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint64_t_fmt_4:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_4(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c
index 2cd9dec6232..0293055c3bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint8_t_fmt_5:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_5(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c
index 7836d0d72f8..e1f3b00736b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint16_t_fmt_5:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_5(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c
index 137f79f0b55..28744069474 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint32_t_fmt_5:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_5(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
index d853cec7935..a7148c1228c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint16_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_1(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c
index 74d585560a0..92167185035 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint64_t_fmt_5:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_5(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
index 8c32916f622..8569956cd54 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint8_t_fmt_6:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_6(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
index 3c41500bf06..ae97fece59b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
@@ -1,18 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint16_t_fmt_6:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_6(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
index 00dc2babe46..222d1ab68ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint32_t_fmt_6:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_6(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c
index 43049fd86cb..7a8843389e3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint64_t_fmt_6:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_6(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
index bcb01f02f20..b42031230aa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint8_t_fmt_7:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_7(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c
index d4304d58511..f68c5bfd2c5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint16_t_fmt_7:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_7(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c
index 923b658a613..ef6bba3e4b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint32_t_fmt_7:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_7(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c
index 20d0d1ba95e..cc60058799b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint64_t_fmt_7:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_7(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
index bff69557438..f0c5289764f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
@@ -1,18 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint8_t_fmt_8:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_8(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c
index afc8e5dbadb..8a55a01b02e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint32_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_1(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c
index 874d26d8887..988d97a3428 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint16_t_fmt_8:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_8(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c
index fe7ed2647da..9f702c68baa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint32_t_fmt_8:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_8(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c
index a00412e81dd..a90fe6a8c36 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint64_t_fmt_8:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_8(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c
index f680a31158d..9ac3524c2c9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint64_t_fmt_1:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_1(uint64_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
index 64fc4092e83..536cade5753 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint8_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_2(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
index a4eae4c7a00..58668229366 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint16_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_2(uint16_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c
index d000e8c5810..4b8b3c92b63 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint32_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_2(uint32_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c
index d25820fd897..0f135392914 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint64_t_fmt_2:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_2(uint64_t)
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c
index 42723a07a76..73afb203a83 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c
@@ -1,18 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_uint8_t_fmt_3:
-** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_FMT_3(uint8_t)
/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c
index d7e955ee86e..ac2be718913 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-1.c
@@ -1,14 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_imm9_uint8_t_fmt_1:
-** ...
-** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*9
-** ...
-*/
DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c
index b6b605ac615..c6db8073bfa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c
@@ -1,14 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_imm15_uint16_t_fmt_3:
-** ...
-** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*15
-** ...
-*/
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 15)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c
index 6da86a1abe1..517db1dc8c6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c
@@ -1,14 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_imm33u_uint32_t_fmt_3:
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 33u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c
index b6ff5a6d5d6..318cafcb10c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c
@@ -1,14 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_imm129ull_uint64_t_fmt_3:
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 129ull)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c
index a9439dff39f..db6a2801849 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-13.c
@@ -1,14 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_imm9u_uint8_t_fmt_4:
-** ...
-** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*9
-** ...
-*/
DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint8_t, 9u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c
index dbe47497599..02c10fa4a26 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-14.c
@@ -1,14 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_imm15_uint16_t_fmt_4:
-** ...
-** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*15
-** ...
-*/
DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint16_t, 15)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c
index 0ac2e1b2942..7cde4c9d378 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c
@@ -1,14 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_imm33u_uint32_t_fmt_4:
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint32_t, 33u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c
index 9574966401a..e418d6b47eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-16.c
@@ -1,14 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_imm129ull_uint64_t_fmt_4:
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_IMM_FMT_4(uint64_t, 129ull)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c
index 4c301273f12..00ff60baa76 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-2.c
@@ -1,14 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_imm15_uint16_t_fmt_1:
-** ...
-** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*15
-** ...
-*/
DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint16_t, 15)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c
index df2394a4f4e..281ce2a1db5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-3.c
@@ -1,14 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_imm33_uint32_t_fmt_1:
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint32_t, 33)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c
index 549d616a05e..391d2db32a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-4.c
@@ -1,14 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_imm129_uint64_t_fmt_1:
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_IMM_FMT_1(uint64_t, 129)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c
index 2819d6d1393..54fcbd145a7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c
@@ -1,14 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_imm9_uint8_t_fmt_2:
-** ...
-** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*9
-** ...
-*/
DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint8_t, 9)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c
index a76cb9b8cc6..e50b7b1e13f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c
@@ -1,14 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_imm15_uint16_t_fmt_2:
-** ...
-** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*15
-** ...
-*/
DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint16_t, 15)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c
index 66bfa6cba5a..341226838a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c
@@ -1,14 +1,8 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_imm33_uint32_t_fmt_2:
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint32_t, 33)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c
index a35344fedc8..870213eda39 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c
@@ -1,14 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_imm129_uint64_t_fmt_2:
-** ...
-** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
-** ...
-*/
DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint64_t, 129)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c
index 15e0a0567d4..de567394389 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c
@@ -1,14 +1,9 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
-/* { dg-skip-if "" { *-*-* } { "-flto" } } */
-/* { dg-final { check-function-bodies "**" "" } } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
-/*
-** vec_sat_u_add_imm9u_uint8_t_fmt_3:
-** ...
-** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*9
-** ...
-*/
DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 9u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */
+/* { dg-final { scan-assembler-times {vsaddu\.vi} 1 } } */