diff mbox series

[v1,2/2] RISC-V: Add testcases for form 3 of signed vector SAT_ADD

Message ID 20240921142246.1949434-1-pan2.li@intel.com
State New
Headers show
Series [v1,1/2] Match: Support form 3 for vector signed integer .SAT_ADD | expand

Commit Message

Li, Pan2 Sept. 21, 2024, 2:22 p.m. UTC 
From: Pan Li <pan2.li@intel.com>

Form 3:
  #define DEF_VEC_SAT_S_ADD_FMT_3(T, UT, MIN, MAX)                     \
  void __attribute__((noinline))                                       \
  vec_sat_s_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        T sum;                                                         \
        bool overflow = __builtin_add_overflow (x, y, &sum);           \
        out[i] = overflow ? x < 0 ? MIN : MAX : sum;                   \
      }                                                                \
  }

DEF_VEC_SAT_S_ADD_FMT_3 (int8_t, uint8_t, INT8_MIN, INT8_MAX)

The below test are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vec_sat_arith.h: Add test helper macros.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-10.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-11.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-12.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-9.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-10.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-11.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-12.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-9.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 .../rvv/autovec/binop/vec_sat_s_add-10.c      |  9 ++++++++
 .../rvv/autovec/binop/vec_sat_s_add-11.c      |  9 ++++++++
 .../rvv/autovec/binop/vec_sat_s_add-12.c      |  9 ++++++++
 .../riscv/rvv/autovec/binop/vec_sat_s_add-9.c |  9 ++++++++
 .../rvv/autovec/binop/vec_sat_s_add-run-10.c  | 17 ++++++++++++++
 .../rvv/autovec/binop/vec_sat_s_add-run-11.c  | 17 ++++++++++++++
 .../rvv/autovec/binop/vec_sat_s_add-run-12.c  | 17 ++++++++++++++
 .../rvv/autovec/binop/vec_sat_s_add-run-9.c   | 17 ++++++++++++++
 .../riscv/rvv/autovec/vec_sat_arith.h         | 22 +++++++++++++++++++
 9 files changed, 126 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-9.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-9.c

Comments

Robin Dapp Sept. 24, 2024, 12:39 p.m. UTC | #1 
LGTM (in case you haven't committed it yet).
Li, Pan2 Sept. 24, 2024, 1:11 p.m. UTC | #2 
Thanks Robin, this depends on [PATCH 1/2] of match.pd change, will commit it after that.

Pan

-----Original Message-----
From: Robin Dapp <rdapp.gcc@gmail.com> 
Sent: Tuesday, September 24, 2024 8:40 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
Cc: richard.guenther@gmail.com; Tamar.Christina@arm.com; juzhe.zhong@rivai.ai; kito.cheng@gmail.com; jeffreyalaw@gmail.com; Robin Dapp <rdapp.gcc@gmail.com>
Subject: Re: [PATCH v1 2/2] RISC-V: Add testcases for form 3 of signed vector SAT_ADD

LGTM (in case you haven't committed it yet).
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-10.c
new file mode 100644
index 00000000000..5dfecdb1732
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-10.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-11.c
new file mode 100644
index 00000000000..ebf825e0dd8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-11.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-12.c
new file mode 100644
index 00000000000..82b29a089f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-12.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-9.c
new file mode 100644
index 00000000000..242ebb28d3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-9.c
@@ -0,0 +1,9 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+
+#include "../vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */
+/* { dg-final { scan-assembler-times {vsadd\.vv} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-10.c
new file mode 100644
index 00000000000..2f73271b771
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-10.c
@@ -0,0 +1,17 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T  int16_t
+#define T1 int16_t
+#define T2 uint16_t
+
+DEF_VEC_SAT_S_ADD_FMT_3_WRAP (T1, T2, INT16_MIN, INT16_MAX)
+
+#define test_data          TEST_BINARY_DATA_NAME_WRAP(T, T, ssadd)
+#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \
+  RUN_VEC_SAT_S_ADD_FMT_3_WRAP(T, out, op_1, op_2, N)
+
+#include "vec_sat_binary_vvv_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-11.c
new file mode 100644
index 00000000000..bcb4d453955
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-11.c
@@ -0,0 +1,17 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T  int32_t
+#define T1 int32_t
+#define T2 uint32_t
+
+DEF_VEC_SAT_S_ADD_FMT_3_WRAP (T1, T2, INT32_MIN, INT32_MAX)
+
+#define test_data          TEST_BINARY_DATA_NAME_WRAP(T, T, ssadd)
+#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \
+  RUN_VEC_SAT_S_ADD_FMT_3_WRAP(T, out, op_1, op_2, N)
+
+#include "vec_sat_binary_vvv_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-12.c
new file mode 100644
index 00000000000..7c565706bfe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-12.c
@@ -0,0 +1,17 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T  int64_t
+#define T1 int64_t
+#define T2 uint64_t
+
+DEF_VEC_SAT_S_ADD_FMT_3_WRAP (T1, T2, INT64_MIN, INT64_MAX)
+
+#define test_data          TEST_BINARY_DATA_NAME_WRAP(T, T, ssadd)
+#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \
+  RUN_VEC_SAT_S_ADD_FMT_3_WRAP(T, out, op_1, op_2, N)
+
+#include "vec_sat_binary_vvv_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-9.c
new file mode 100644
index 00000000000..28c96dbcac9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_s_add-run-9.c
@@ -0,0 +1,17 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T  int8_t
+#define T1 int8_t
+#define T2 uint8_t
+
+DEF_VEC_SAT_S_ADD_FMT_3_WRAP (T1, T2, INT8_MIN, INT8_MAX)
+
+#define test_data          TEST_BINARY_DATA_NAME_WRAP(T, T, ssadd)
+#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \
+  RUN_VEC_SAT_S_ADD_FMT_3_WRAP(T, out, op_1, op_2, N)
+
+#include "vec_sat_binary_vvv_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
index 1bac47e67a5..96575c6a11b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vec_sat_arith.h
@@ -260,6 +260,23 @@  vec_sat_s_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
 #define DEF_VEC_SAT_S_ADD_FMT_2_WRAP(T, UT, MIN, MAX) \
   DEF_VEC_SAT_S_ADD_FMT_2(T, UT, MIN, MAX)
 
+#define DEF_VEC_SAT_S_ADD_FMT_3(T, UT, MIN, MAX)                     \
+void __attribute__((noinline))                                       \
+vec_sat_s_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \
+{                                                                    \
+  unsigned i;                                                        \
+  for (i = 0; i < limit; i++)                                        \
+    {                                                                \
+      T x = op_1[i];                                                 \
+      T y = op_2[i];                                                 \
+      T sum;                                                         \
+      bool overflow = __builtin_add_overflow (x, y, &sum);           \
+      out[i] = overflow ? x < 0 ? MIN : MAX : sum;                   \
+    }                                                                \
+}
+#define DEF_VEC_SAT_S_ADD_FMT_3_WRAP(T, UT, MIN, MAX) \
+  DEF_VEC_SAT_S_ADD_FMT_3(T, UT, MIN, MAX)
+
 #define RUN_VEC_SAT_S_ADD_FMT_1(T, out, op_1, op_2, N) \
   vec_sat_s_add_##T##_fmt_1(out, op_1, op_2, N)
 #define RUN_VEC_SAT_S_ADD_FMT_1_WRAP(T, out, op_1, op_2, N) \
@@ -270,6 +287,11 @@  vec_sat_s_add_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \
 #define RUN_VEC_SAT_S_ADD_FMT_2_WRAP(T, out, op_1, op_2, N) \
   RUN_VEC_SAT_S_ADD_FMT_2(T, out, op_1, op_2, N)
 
+#define RUN_VEC_SAT_S_ADD_FMT_3(T, out, op_1, op_2, N) \
+  vec_sat_s_add_##T##_fmt_3(out, op_1, op_2, N)
+#define RUN_VEC_SAT_S_ADD_FMT_3_WRAP(T, out, op_1, op_2, N) \
+  RUN_VEC_SAT_S_ADD_FMT_3(T, out, op_1, op_2, N)
+
 /******************************************************************************/
 /* Saturation Sub (Unsigned and Signed)                                       */
 /******************************************************************************/