| Message ID | 20240919041112.3797328-1-pan2.li@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v5,1/4] Match: Add interface match_cond_with_binary_phi for true/false arg | expand |
> This patch would like fix the dump check times of vector SAT_ADD. The > middle-end change makes the match times from 2 to 4 times. > > The below test suites are passed for this patch. > * The rv64gcv fully regression test. That's OK. And I think testsuite fixup patches like this you can consider "obvious" as long as you're sure the underlying reason is understood. In particular as you have been working in the saturating space for a while now. So for the future I'd suggest you post those with a remark that you think they're obvious and going to commit in a day (or some other reasonable timeframe) if there are no complaints.
> So for the future I'd suggest you post those with a remark that you think > they're obvious and going to commit in a day (or some other reasonable > timeframe) if there are no complaints. Oh, I see. Thanks Robin for reminding. That would be perfect. Do you have any best practices for the remark "obvious"? Like [NFC] in subject to give some hit for not-function-change, maybe take [TBO] stand for to-be-obvious or something like that. Pan -----Original Message----- From: Robin Dapp <rdapp.gcc@gmail.com> Sent: Thursday, September 19, 2024 4:26 PM To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com; Tamar.Christina@arm.com; juzhe.zhong@rivai.ai; kito.cheng@gmail.com; jeffreyalaw@gmail.com; Robin Dapp <rdapp.gcc@gmail.com> Subject: Re: [PATCH v5 4/4] RISC-V: Fix vector SAT_ADD dump check due to middle-end change > This patch would like fix the dump check times of vector SAT_ADD. The > middle-end change makes the match times from 2 to 4 times. > > The below test suites are passed for this patch. > * The rv64gcv fully regression test. That's OK. And I think testsuite fixup patches like this you can consider "obvious" as long as you're sure the underlying reason is understood. In particular as you have been working in the saturating space for a while now. So for the future I'd suggest you post those with a remark that you think they're obvious and going to commit in a day (or some other reasonable timeframe) if there are no complaints.
On 9/19/24 4:11 AM, Li, Pan2 wrote: >> So for the future I'd suggest you post those with a remark that you think >> they're obvious and going to commit in a day (or some other reasonable >> timeframe) if there are no complaints. > > Oh, I see. Thanks Robin for reminding. > > That would be perfect. Do you have any best practices for the remark "obvious"? > Like [NFC] in subject to give some hit for not-function-change, maybe take [TBO] stand for to-be-obvious or something like that. Typically we say something like "pushing as obvious". jeff
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c index c525ba97c52..47dd5012cc6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_6(uint8_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c index 41372d08e52..df8d5a8d275 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_6(uint16_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c index dddebb54426..f286bd10e4b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_6(uint32_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c index ad5162d10a0..307ff36cc35 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_6(uint64_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c index 39c20b3cea6..3218962724c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_7(uint8_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c index 6eefaeebf31..922df02278d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_7(uint16_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c index 78beb1bd39e..7653f81531c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_7(uint32_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c index 369fa296d08..18803afd19a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_7(uint64_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c index e827cdd1657..e95d6f73c38 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_8(uint8_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c index af16f48e228..34e10236381 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_8(uint16_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c index 0a8eabfbad1..7fc5e73fe1d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_8(uint32_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c index 38cbdfbcf07..9684fdf37f7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_8(uint64_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c index fe8a5a8262d..96787fc15e2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_2(uint8_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c index 1aeb24eed0d..f155d7c47c7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_2(uint16_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c index 0d2b0e4ab80..5fdb67cc1ca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_2(uint32_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c index 168c269f75e..eee4d902fb5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c @@ -15,4 +15,4 @@ */ DEF_VEC_SAT_U_ADD_FMT_2(uint64_t) -/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 2 "expand" } } */ +/* { dg-final { scan-rtl-dump-times ".SAT_ADD " 4 "expand" } } */