diff mbox series

[v3,1/5] Genmatch: Add control flow graph match for case 0 and case 1

Message ID 20240911062945.3358247-1-pan2.li@intel.com
State New
Headers show
Series [v3,1/5] Genmatch: Add control flow graph match for case 0 and case 1 | expand

Commit Message

Li, Pan2 Sept. 11, 2024, 6:29 a.m. UTC 
From: Pan Li <pan2.li@intel.com>

The gen_phi_on_cond can only support below control flow for cond
from day 1.  Aka:

+------+
| def  |
| ...  |       +-----+
| cond |------>| def |
+------+       | ... |
   |           +-----+
   |              |
   v              |
+-----+           |
| PHI |<----------+
+-----+

Unfortunately, there will be more scenarios of control flow on PHI.
For example as below:

T __attribute__((noinline))                            \
sat_s_add_##T##_fmt_3 (T x, T y)                       \
{                                                      \
  T sum;                                               \
  bool overflow = __builtin_add_overflow (x, y, &sum); \
  return overflow ? x < 0 ? MIN : MAX : sum;           \
}

DEF_SAT_S_ADD_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX)

With expanded RTL like below.
   3   │
   4   │ __attribute__((noinline))
   5   │ int8_t sat_s_add_int8_t_fmt_3 (int8_t x, int8_t y)
   6   │ {
   7   │   signed char _1;
   8   │   signed char _2;
   9   │   int8_t _3;
  10   │   __complex__ signed char _6;
  11   │   _Bool _8;
  12   │   signed char _9;
  13   │   signed char _10;
  14   │   signed char _11;
  15   │
  16   │ ;;   basic block 2, loop depth 0
  17   │ ;;    pred:       ENTRY
  18   │   _6 = .ADD_OVERFLOW (x_4(D), y_5(D));
  19   │   _2 = IMAGPART_EXPR <_6>;
  20   │   if (_2 != 0)
  21   │     goto <bb 4>; [50.00%]
  22   │   else
  23   │     goto <bb 3>; [50.00%]
  24   │ ;;    succ:       4
  25   │ ;;                3
  26   │
  27   │ ;;   basic block 3, loop depth 0
  28   │ ;;    pred:       2
  29   │   _1 = REALPART_EXPR <_6>;
  30   │   goto <bb 5>; [100.00%]
  31   │ ;;    succ:       5
  32   │
  33   │ ;;   basic block 4, loop depth 0
  34   │ ;;    pred:       2
  35   │   _8 = x_4(D) < 0;
  36   │   _9 = (signed char) _8;
  37   │   _10 = -_9;
  38   │   _11 = _10 ^ 127;
  39   │ ;;    succ:       5
  40   │
  41   │ ;;   basic block 5, loop depth 0
  42   │ ;;    pred:       3
  43   │ ;;                4
  44   │   # _3 = PHI <_1(3), _11(4)>
  45   │   return _3;
  46   │ ;;    succ:       EXIT
  47   │
  48   │ }

The above code will have below control flow which is not supported by
the gen_phi_on_cond.

+------+
| def  |
| ...  |       +-----+
| cond |------>| def |
+------+       | ... |
   |           +-----+
   |              |
   v              |
+-----+           |
| def |           |
| ... |           |
+-----+           |
   |              |
   |              |
   v              |
+-----+           |
| PHI |<----------+
+-----+

This patch would like to add support above control flow matching for
the gen_phi_on_cond.

The below testsuites are passed for this patch:
* The rv64gcv fully regression test.
* The x86 bootstrap test.
* The x86 fully regression test.

gcc/ChangeLog:

	* gimple-match-head.cc (match_control_flow_graph_case_0): Add
	new func impl to match case 0 of cfg.
	(match_control_flow_graph_case_1): Ditto but for case 1.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/gimple-match-head.cc | 115 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 115 insertions(+)
diff mbox series

Patch

diff --git a/gcc/gimple-match-head.cc b/gcc/gimple-match-head.cc
index 924d3f1e710..c51728ae742 100644
--- a/gcc/gimple-match-head.cc
+++ b/gcc/gimple-match-head.cc
@@ -375,3 +375,118 @@  gimple_bitwise_inverted_equal_p (tree expr1, tree expr2, bool &wascmp, tree (*va
     return true;
   return false;
 }
+
+/*
+ * Return TRUE if the cfg matches the below layout by the given b2 in
+ * the first argument.  Or return FALSE.
+ *
+ * If return TRUE, the output argument b_out will be updated to the b0
+ * block as below example.
+ *
+ * If return FALSE, the output argument b_out will be NULL_BLOCK.
+ *
+ *    |
+ *    |
+ *    v
+ * +------+
+ * | b0:  |
+ * | def  |       +-----+
+ * | ...  |       | b1: |
+ * | cond |------>| def |
+ * +------+       | ... |
+ *    |           +-----+
+ *    |              |
+ *    v              |
+ * +-----+           |
+ * | b2: |           |
+ * | def |<----------+
+ * +-----+
+ */
+static inline bool
+match_control_flow_graph_case_0 (basic_block b2, basic_block *b_out)
+{
+  *b_out = NULL;
+
+  if (EDGE_COUNT (b2->preds) != 2)
+    return false;
+
+  basic_block pred_0 = EDGE_PRED (b2, 0)->src;
+  basic_block pred_1 = EDGE_PRED (b2, 1)->src;
+
+  if (pred_0 == NULL || pred_1 == NULL)
+    return false;
+
+  if (!(EDGE_COUNT (pred_0->succs) == 2 && EDGE_COUNT (pred_1->succs) == 1)
+     && !(EDGE_COUNT (pred_0->succs) == 1 && EDGE_COUNT (pred_1->succs) == 2))
+    return false;
+
+  basic_block b0 = EDGE_COUNT (pred_0->succs) == 2 ? pred_0 : pred_1;
+  basic_block b1 = EDGE_COUNT (pred_0->succs) == 1 ? pred_0 : pred_1;
+
+  if (EDGE_COUNT (b1->preds) != 1 || EDGE_PRED (b1, 0)->src != b0)
+    return false;
+
+  *b_out = b0;
+  return true;
+}
+
+/*
+ * Return TRUE if the cfg matches the below layout by the given b3 in
+ * the first argument.  Or return FALSE.
+ *
+ * If return TRUE, the output argument b_out will be updated to the b0
+ * block as below example.
+ *
+ * If return FALSE, the output argument b_out will be NULL.
+ *
+ *    |
+ *    |
+ *    v
+ * +------+
+ * | b0:  |
+ * | ...  |       +-----+
+ * | cond |------>| b2: |
+ * +------+       | ... |
+ *    |           +-----+
+ *    |              |
+ *    v              |
+ * +-----+           |
+ * | b1: |           |
+ * | ... |           |
+ * +-----+           |
+ *    |              |
+ *    |              |
+ *    v              |
+ * +-----+           |
+ * | b3: |<----------+
+ * | ... |
+ * +-----+
+ */
+static inline bool
+match_control_flow_graph_case_1 (basic_block b3, basic_block *b_out)
+{
+  *b_out = NULL;
+
+  if (EDGE_COUNT (b3->preds) != 2)
+    return false;
+
+  basic_block b1 = EDGE_PRED (b3, 0)->src;
+  basic_block b2 = EDGE_PRED (b3, 1)->src;
+
+  if (b1 == NULL || b2 == NULL)
+    return false;
+
+  if (EDGE_COUNT (b1->succs) != 1
+      || EDGE_COUNT (b1->preds) != 1
+      || EDGE_COUNT (b2->succs) != 1
+      || EDGE_COUNT (b2->preds) != 1)
+    return false;
+
+  basic_block b0 = EDGE_PRED (b1, 0)->src;
+
+  if (EDGE_COUNT (b0->succs) != 2 || EDGE_PRED (b2, 0)->src != b0)
+    return false;
+
+  *b_out = b0;
+  return true;
+}