diff mbox series

[v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32.

Message ID 20240909091035.1241-1-jinma@linux.alibaba.com
State New
Headers show
Series [v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32. | expand

Commit Message

Jin Ma Sept. 9, 2024, 9:10 a.m. UTC 
gcc/ChangeLog:

	* config/riscv/riscv.md: Change "truncate" to unspec for the Zfa extension on rv32.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/zfa-fmovh-fmovp-bug.c: New test.
---
 gcc/config/riscv/riscv.md                        | 16 +++++++++-------
 .../gcc.target/riscv/zfa-fmovh-fmovp-bug.c       |  9 +++++++++
 2 files changed, 18 insertions(+), 7 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp-bug.c

Comments

Jin Ma Sept. 14, 2024, 3:17 a.m. UTC | #1 
Hi, any more comments about this patch to fix zfa's ICE?

BR,
Jin
Jeff Law Sept. 18, 2024, 2:55 p.m. UTC | #2 
On 9/13/24 9:17 PM, Jin Ma wrote:
> 
> Hi, any more comments about this patch to fix zfa's ICE?
Sorry, need to correct the final conclusion in my last message.  We 
should go with the v3 patch, not the v2 patch.
jeff
Jeff Law Sept. 18, 2024, 2:58 p.m. UTC | #3 
On 9/9/24 3:10 AM, Jin Ma wrote:
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv.md: Change "truncate" to unspec for the Zfa extension on rv32.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/zfa-fmovh-fmovp-bug.c: New test.
I've pushed this version to the trunk.

Thanks,
jeff
Jin Ma Sept. 19, 2024, 3:12 a.m. UTC | #4 
> > gcc/ChangeLog:
> >
> >  * config/riscv/riscv.md: Change "truncate" to unspec for the Zfa extension on rv32.
> >
> > gcc/testsuite/ChangeLog:
> >
> >  * gcc.target/riscv/zfa-fmovh-fmovp-bug.c: New test.
> I've pushed this version to the trunk.
> 
> Thanks,
> jeff

Thanks Jeff and Christoph for the review work on this :)

BR
Jin
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 9f94b5aa0232..13b360d6a701 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -56,6 +56,8 @@  (define_c_enum "unspec" [
   UNSPEC_FLT_QUIET
   UNSPEC_FLE_QUIET
   UNSPEC_COPYSIGN
+  UNSPEC_FMV_X_W
+  UNSPEC_FMVH_X_D
   UNSPEC_RINT
   UNSPEC_ROUND
   UNSPEC_FLOOR
@@ -2627,8 +2629,9 @@  (define_insn "*movdf_softfloat"
 
 (define_insn "movsidf2_low_rv32"
   [(set (match_operand:SI      0 "register_operand" "=  r")
-	(truncate:SI
-	    (match_operand:DF 1 "register_operand"  "zmvf")))]
+	(unspec:SI
+	    [(match_operand:DF 1 "register_operand" "zmvf")]
+	UNSPEC_FMV_X_W))]
   "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
   "fmv.x.w\t%0,%1"
   [(set_attr "move_type" "fmove")
@@ -2637,11 +2640,10 @@  (define_insn "movsidf2_low_rv32"
 
 
 (define_insn "movsidf2_high_rv32"
-  [(set (match_operand:SI      0 "register_operand"    "=  r")
-	(truncate:SI
-            (lshiftrt:DF
-                (match_operand:DF 1 "register_operand" "zmvf")
-                (const_int 32))))]
+  [(set (match_operand:SI      0 "register_operand" "=  r")
+	(unspec:SI
+	    [(match_operand:DF 1 "register_operand" "zmvf")]
+	UNSPEC_FMVH_X_D))]
   "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
   "fmvh.x.d\t%0,%1"
   [(set_attr "move_type" "fmove")
diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp-bug.c b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp-bug.c
new file mode 100644
index 000000000000..e00047b09e3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp-bug.c
@@ -0,0 +1,9 @@ 
+/* Test that we do not have ice when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_zfa -mabi=ilp32d -O2 -g" } */
+
+unsigned int
+foo (double a) {
+  unsigned int tt = *(unsigned long long *)&a & 0xffff;
+  return tt;
+}