Show patches with: Submitter = Jin Ma       |    State = Action Required       |    Archived = No       |   59 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v2,2/2] RISC-V: Fix ICE due to inconsistency of RVV intrinsic list in lto and cc1. RISC-V: Fix ICE for rvv in lto - - - - --- 2024-09-10 Jin Ma New
[v2,1/2] RISC-V: Fix ICE caused by early ggc_free on DECL for RVV intrinsics in LTO. [v2,1/2] RISC-V: Fix ICE caused by early ggc_free on DECL for RVV intrinsics in LTO. - - - - --- 2024-09-10 Jin Ma New
[v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32. [v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32. - - - - --- 2024-09-09 Jin Ma New
[v4] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector [v4] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector - - - - --- 2024-09-06 Jin Ma New
RISC-V: Fix ICE for rvv in lto RISC-V: Fix ICE for rvv in lto - - - - --- 2024-09-06 Jin Ma New
[v2] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32. [v2] RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32. - - - - --- 2024-09-06 Jin Ma New
RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32. RISC-V: Fixed incorrect semantic description in DF to DI pattern in the Zfa extension on rv32. - - - - --- 2024-09-06 Jin Ma New
[v3] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector [v3] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector - - - - --- 2024-09-06 Jin Ma New
[v2] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector [v2] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector - - - - --- 2024-09-06 Jin Ma New
RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for xtheadvector RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for xtheadvector - - - - --- 2024-09-06 Jin Ma New
[v2] RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker [v2] RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker - - - - --- 2024-08-12 Jin Ma New
RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker - - - - --- 2024-08-09 Jin Ma New
[v2] RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics [v2] RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics - - - - --- 2024-08-08 Jin Ma New
RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics - - - - --- 2024-08-07 Jin Ma New
RISC-V: Delete duplicate '#define RISCV_DWARF_VLENB' RISC-V: Delete duplicate '#define RISCV_DWARF_VLENB' - - - - --- 2024-08-03 Jin Ma New
haifa-sched: Avoid the fusion priority of the fused insn to affect the subsequent insn sequence. haifa-sched: Avoid the fusion priority of the fused insn to affect the subsequent insn sequence. - - - - --- 2024-06-05 Jin Ma New
[v2] RISC-V: THEAD: Fix improper immediate value for MODIFY_DISP instruction on 32-bit systems. [v2] RISC-V: THEAD: Fix improper immediate value for MODIFY_DISP instruction on 32-bit systems. - - - - --- 2024-01-29 Jin Ma New
RISC-V: THEAD: Fix improper immediate value for MODIFY_DISP instruction on 32-bit systems. RISC-V: THEAD: Fix improper immediate value for MODIFY_DISP instruction on 32-bit systems. - - - - --- 2024-01-29 Jin Ma New
RISC-V: THEAD: Fix ICE caused by split optimizations for XTheadFMemIdx. RISC-V: THEAD: Fix ICE caused by split optimizations for XTheadFMemIdx. - - - - --- 2024-01-11 Jin Ma New
Support libcall __float{, un}sibf by SF when it is not supported for _bf16 Support libcall __float{, un}sibf by SF when it is not supported for _bf16 - - - - --- 2023-12-20 Jin Ma New
[v2] RISC-V: T-HEAD: Add support for the XTheadInt ISA extension [v2] RISC-V: T-HEAD: Add support for the XTheadInt ISA extension - - - - --- 2023-11-17 Jin Ma New
[v2] RISC-V: Fixbug for that XTheadMemPair causes interrupt to fail. [v2] RISC-V: Fixbug for that XTheadMemPair causes interrupt to fail. - - - - --- 2023-11-10 Jin Ma New
RISC-V: Fix bug that XTheadMemPair extension caused fcsr not to be saved and restored before and af… RISC-V: Fix bug that XTheadMemPair extension caused fcsr not to be saved and restored before and af… - - 1 - --- 2023-11-10 Jin Ma New
RISC-V: Fix the illegal operands for the XTheadMemidx extension. RISC-V: Fix the illegal operands for the XTheadMemidx extension. - - - - --- 2023-11-09 Jin Ma New
riscv: thead: Add support for the XTheadInt ISA extension riscv: thead: Add support for the XTheadInt ISA extension - - - - --- 2023-11-07 Jin Ma New
[RFC,2/2] RISC-V: Add 'Zfbfmin' extension. [RFC,1/2] RISC-V: Add support for _Bfloat16. - - - - --- 2023-09-19 Jin Ma New
[RFC,1/2] RISC-V: Add support for _Bfloat16. [RFC,1/2] RISC-V: Add support for _Bfloat16. - - - - --- 2023-09-19 Jin Ma New
RISC-V: Added zvfh support for zfa extensions. RISC-V: Added zvfh support for zfa extensions. - - - - --- 2023-08-29 Jin Ma New
[v2] In the pipeline, USE or CLOBBER should delay execution if it starts a new live range. [v2] In the pipeline, USE or CLOBBER should delay execution if it starts a new live range. - - - - --- 2023-08-14 Jin Ma New
[v10] RISC-V: Add support for the Zfa extension [v10] RISC-V: Add support for the Zfa extension - - - - --- 2023-08-14 Jin Ma New
[v4] RISC-V: Fixbug for fsflags instruction error using immediate. [v4] RISC-V: Fixbug for fsflags instruction error using immediate. - - - - --- 2023-07-26 Jin Ma New
[v3] RISC-V: Fixbug for fsflags instruction error using immediate. [v3] RISC-V: Fixbug for fsflags instruction error using immediate. - - - - --- 2023-07-26 Jin Ma New
[v2] RISC-V: Fixbug for fsflags instruction error using immediate. [v2] RISC-V: Fixbug for fsflags instruction error using immediate. - - - - --- 2023-07-25 Jin Ma New
RISC-V: Fixbug for fsflags instruction error using immediate. RISC-V: Fixbug for fsflags instruction error using immediate. - - - - --- 2023-07-25 Jin Ma New
[v2] RISC-V: Save and restore FCSR in interrupt functions to avoid program errors. [v2] RISC-V: Save and restore FCSR in interrupt functions to avoid program errors. - - - - --- 2023-06-14 Jin Ma New
RISC-V: Save and restore FCSR in interrupt functions to avoid program errors. RISC-V: Save and restore FCSR in interrupt functions to avoid program errors. - - - - --- 2023-06-13 Jin Ma New
RISC-V: Handle no_insn in TARGET_SCHED_VARIABLE_ISSUE. RISC-V: Handle no_insn in TARGET_SCHED_VARIABLE_ISSUE. - - - - --- 2023-05-29 Jin Ma New
In the pipeline, UNRECOG INSN is not executed in advance if it starts a live range. In the pipeline, UNRECOG INSN is not executed in advance if it starts a live range. - - - - --- 2023-05-29 Jin Ma New
RISC-V: Add the option "-mno-multilib-check" to disable multilib checks. RISC-V: Add the option "-mno-multilib-check" to disable multilib checks. - - - - --- 2023-05-26 Jin Ma New
RISC-V: In pipeline scheduling, insns should not be fusion in different BB blocks. RISC-V: In pipeline scheduling, insns should not be fusion in different BB blocks. - - - - --- 2023-05-25 Jin Ma New
RISC-V: Add the option "-mdisable-multilib-check" to avoid multilib checks breaking the compilation. RISC-V: Add the option "-mdisable-multilib-check" to avoid multilib checks breaking the compilation. - - - - --- 2023-05-23 Jin Ma New
RISC-V: Remove trailing spaces on lines. RISC-V: Remove trailing spaces on lines. - - - - --- 2023-05-17 Jin Ma New
Fix type error of 'switch (SUBREG_BYTE (op)).' Fix type error of 'switch (SUBREG_BYTE (op)).' - - - - --- 2023-05-17 Jin Ma New
[v9] RISC-V: Add the 'zfa' extension, version 0.2 [v9] RISC-V: Add the 'zfa' extension, version 0.2 - - - - --- 2023-05-15 Jin Ma New
[v8] RISC-V: Add the 'zfa' extension, version 0.2. [v8] RISC-V: Add the 'zfa' extension, version 0.2. - - - 1 --- 2023-04-19 Jin Ma New
Fixed typo. Fixed typo. - - - - --- 2023-04-18 Jin Ma New
RISC-V: Adjust the parsing order of extensions to be consistent with riscv-spec and binutils. RISC-V: Adjust the parsing order of extensions to be consistent with riscv-spec and binutils. - - - - --- 2023-04-18 Jin Ma New
In the ready lists of pipeline, put unrecog insns (such as CLOBBER, USE) at the latest to issue. In the ready lists of pipeline, put unrecog insns (such as CLOBBER, USE) at the latest to issue. - - - - --- 2023-03-23 Jin Ma New
[v6] RISC-V: Add support for experimental zfa extension. [v6] RISC-V: Add support for experimental zfa extension. - - - - --- 2023-03-10 Jin Ma New
RISC-V: Don't report an error until the link phase if suitable multilib isn't found. RISC-V: Don't report an error until the link phase if suitable multilib isn't found. - - - - --- 2023-02-22 Jin Ma New
RISC-V: When the TARGET_COMPUTE_MULTILIB hook is implemented, check the version of each extension. RISC-V: When the TARGET_COMPUTE_MULTILIB hook is implemented, check the version of each extension. - - - - --- 2023-02-22 Jin Ma New
[v1] RISC-V: Change the generation mode of ADJUST_SP_RTX from gen_insn to gen_SET. [v1] RISC-V: Change the generation mode of ADJUST_SP_RTX from gen_insn to gen_SET. - - - - --- 2023-02-03 Jin Ma New
RISC-V: Fix bug of TARGET_COMPUTE_MULTILIB implemented in riscv. RISC-V: Fix bug of TARGET_COMPUTE_MULTILIB implemented in riscv. - - - - --- 2023-02-02 Jin Ma New
[v5,RISCV] Add 'Zfa' extension according to riscv-isa-manual [v5,RISCV] Add 'Zfa' extension according to riscv-isa-manual - - - - --- 2023-02-02 Jin Ma New
[v4,RISCV] Add 'Zfa' extension according to riscv-isa-manual [v4,RISCV] Add 'Zfa' extension according to riscv-isa-manual - - - - --- 2023-01-12 Jin Ma New
[v2,RISCV] Add 'Zfa' extension according to riscv-isa-manual [v2,RISCV] Add 'Zfa' extension according to riscv-isa-manual - - - - --- 2023-01-12 Jin Ma New
[RISCV] Add 'Zfa' extension according to riscv-isa-manual [RISCV] Add 'Zfa' extension according to riscv-isa-manual - - - - --- 2023-01-11 Jin Ma New
[RISCV] Change the generation mode of `adjust_sp_rtx` from gen_insn to gen_SET. [RISCV] Change the generation mode of `adjust_sp_rtx` from gen_insn to gen_SET. - - - - --- 2023-01-06 Jin Ma New
[1/1] Fixed typo in RISCV [1/1] Fixed typo in RISCV - - - - --- 2022-12-23 Jin Ma New