| Message ID | 20240906083232.947-1-jinma@linux.alibaba.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v3] RISC-V: Fix illegal operands "th.vsetvli zero, 0, e32, m8" for XTheadVector | expand |
Sorry, I still don't see assembly check.
juzhe.zhong@rivai.ai
From: Jin Ma
Date: 2024-09-06 16:32
To: gcc-patches
CC: jeffreyalaw; juzhe.zhong; pan2.li; kito.cheng; christoph.muellner; shuizhuyuanluo; pinskia; xry111; jinma.contrib; Jin Ma
Subject: [PATCH v3] RISC-V: Fix illegal operands "th.vsetvli zero,0,e32,m8" for XTheadVector
Since the THeadVector vsetvli does not support vl as an immediate, we
need to convert 0 to zero when outputting asm.
PR target/116592
gcc/ChangeLog:
* config/riscv/thead.cc (th_asm_output_opcode): Change '0' to
"zero"
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/xtheadvector/pr116592.c: New test.
Reported-by: nihui <shuizhuyuanluo@gmail.com>
---
gcc/config/riscv/thead.cc | 4 +--
.../riscv/rvv/xtheadvector/pr116592.c | 36 +++++++++++++++++++
2 files changed, 38 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c
diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc
index 2f1d83fbbc7f..707d91076eb5 100644
--- a/gcc/config/riscv/thead.cc
+++ b/gcc/config/riscv/thead.cc
@@ -960,11 +960,11 @@ th_asm_output_opcode (FILE *asm_out_file, const char *p)
if (strstr (p, "zero,zero"))
return "th.vsetvli\tzero,zero,e%0,%m1";
else
- return "th.vsetvli\tzero,%0,e%1,%m2";
+ return "th.vsetvli\tzero,%z0,e%1,%m2";
}
else
{
- return "th.vsetvli\t%0,%1,e%2,%m3";
+ return "th.vsetvli\t%z0,%z1,e%2,%m3";
}
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c
new file mode 100644
index 000000000000..1350f739c42a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c
@@ -0,0 +1,36 @@
+/* { dg-do assemble } */
+/* { dg-options "-march=rv32gc_zfh_xtheadvector -mabi=ilp32d -O2" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_zfh_xtheadvector -mabi=lp64d -O2" { target { rv64 } } } */
+
+#include <math.h>
+#include <riscv_vector.h>
+
+static vfloat32m8_t atan2_ps(vfloat32m8_t a, vfloat32m8_t b, size_t vl)
+{
+ float tmpx[vl];
+ float tmpy[vl];
+ __riscv_vse32_v_f32m8(tmpx, a, vl);
+ __riscv_vse32_v_f32m8(tmpy, b, vl);
+ for (size_t i = 0; i < vl; i++)
+ {
+ tmpx[i] = atan2(tmpx[i], tmpy[i]);
+ }
+ return __riscv_vle32_v_f32m8(tmpx, vl);
+}
+
+void my_atan2(const float *x, const float *y, float *out, int size)
+{
+ int n = size;
+ while (n > 0)
+ {
+ size_t vl = __riscv_vsetvl_e32m8(n);
+ vfloat32m8_t _x = __riscv_vle32_v_f32m8(x, vl);
+ vfloat32m8_t _y = __riscv_vle32_v_f32m8(y, vl);
+ vfloat32m8_t _out = atan2_ps(_x, _y, vl);
+ __riscv_vse32_v_f32m8(out, _out, vl);
+ n -= vl;
+ x += vl;
+ y += vl;
+ out += vl;
+ }
+}
> Sorry, I still don't see assembly check.
I am very sorry, I uploaded the wrong patch and I tried to correct it :)
By the way, there seems to be no exp here to really test the XTheadVector test cases,
which may have been missed when the XTheadVector extension was first implemented.
Maybe I should write one for that.
BR
Jin
diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc index 2f1d83fbbc7f..707d91076eb5 100644 --- a/gcc/config/riscv/thead.cc +++ b/gcc/config/riscv/thead.cc @@ -960,11 +960,11 @@ th_asm_output_opcode (FILE *asm_out_file, const char *p) if (strstr (p, "zero,zero")) return "th.vsetvli\tzero,zero,e%0,%m1"; else - return "th.vsetvli\tzero,%0,e%1,%m2"; + return "th.vsetvli\tzero,%z0,e%1,%m2"; } else { - return "th.vsetvli\t%0,%1,e%2,%m3"; + return "th.vsetvli\t%z0,%z1,e%2,%m3"; } } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c new file mode 100644 index 000000000000..1350f739c42a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr116592.c @@ -0,0 +1,36 @@ +/* { dg-do assemble } */ +/* { dg-options "-march=rv32gc_zfh_xtheadvector -mabi=ilp32d -O2" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_zfh_xtheadvector -mabi=lp64d -O2" { target { rv64 } } } */ + +#include <math.h> +#include <riscv_vector.h> + +static vfloat32m8_t atan2_ps(vfloat32m8_t a, vfloat32m8_t b, size_t vl) +{ + float tmpx[vl]; + float tmpy[vl]; + __riscv_vse32_v_f32m8(tmpx, a, vl); + __riscv_vse32_v_f32m8(tmpy, b, vl); + for (size_t i = 0; i < vl; i++) + { + tmpx[i] = atan2(tmpx[i], tmpy[i]); + } + return __riscv_vle32_v_f32m8(tmpx, vl); +} + +void my_atan2(const float *x, const float *y, float *out, int size) +{ + int n = size; + while (n > 0) + { + size_t vl = __riscv_vsetvl_e32m8(n); + vfloat32m8_t _x = __riscv_vle32_v_f32m8(x, vl); + vfloat32m8_t _y = __riscv_vle32_v_f32m8(y, vl); + vfloat32m8_t _out = atan2_ps(_x, _y, vl); + __riscv_vse32_v_f32m8(out, _out, vl); + n -= vl; + x += vl; + y += vl; + out += vl; + } +}