| Message ID | 20240902112753.4115540-1-pan2.li@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v1] RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD | expand |
On 9/2/24 5:27 AM, pan2.li@intel.com wrote: > From: Pan Li <pan2.li@intel.com> > > This patch would like to allow the IMM operand of the unsigned > scalar .SAT_ADD. Like the operand 0, the operand 1 of .SAT_ADD > will be zero extended to Xmode before underlying code generation. > > The below test suites are passed for this patch. > * The rv64gcv fully regression test. > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_expand_usadd): Zero extend > the second operand of usadd as the first operand does. > * config/riscv/riscv.md (usadd<m>3): Allow imm operand for > scalar usadd pattern. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/sat_u_add-11.c: Make asm check robust. > * gcc.target/riscv/sat_u_add-15.c: Ditto. > * gcc.target/riscv/sat_u_add-19.c: Ditto. > * gcc.target/riscv/sat_u_add-23.c: Ditto. > * gcc.target/riscv/sat_u_add-3.c: Ditto. > * gcc.target/riscv/sat_u_add-7.c: Ditto. OK jeff
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index d03e51f3a68..4061d2372b4 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -11970,7 +11970,7 @@ riscv_expand_usadd (rtx dest, rtx x, rtx y) rtx xmode_sum = gen_reg_rtx (Xmode); rtx xmode_lt = gen_reg_rtx (Xmode); rtx xmode_x = riscv_gen_zero_extend_rtx (x, mode); - rtx xmode_y = gen_lowpart (Xmode, y); + rtx xmode_y = riscv_gen_zero_extend_rtx (y, mode); rtx xmode_dest = gen_reg_rtx (Xmode); /* Step-1: sum = x + y */ diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 3289ed2155a..4b0be43f436 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -4358,8 +4358,8 @@ (define_insn_and_split "" (define_expand "usadd<mode>3" [(match_operand:ANYI 0 "register_operand") - (match_operand:ANYI 1 "register_operand") - (match_operand:ANYI 2 "register_operand")] + (match_operand:ANYI 1 "reg_or_int_operand") + (match_operand:ANYI 2 "reg_or_int_operand")] "" { riscv_expand_usadd (operands[0], operands[1], operands[2]); diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-11.c index e248aeafa8e..bd830ececad 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-11.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-11.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_3: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-15.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-15.c index bb8b991a84e..de615a6225e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-15.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-15.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_4: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c index 7e4ae12f2f5..2b793e2f8fd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-19.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_5: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-23.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-23.c index 49bbb74a401..5de086e1138 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-23.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-23.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_6: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-3.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-3.c index cd15dc96450..bd7ccb2a8c7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-3.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-3.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_1: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add-7.c b/gcc/testsuite/gcc.target/riscv/sat_u_add-7.c index a0b79b15ac4..496d5cfbe81 100644 --- a/gcc/testsuite/gcc.target/riscv/sat_u_add-7.c +++ b/gcc/testsuite/gcc.target/riscv/sat_u_add-7.c @@ -8,7 +8,7 @@ ** sat_u_add_uint32_t_fmt_2: ** slli\s+[atx][0-9]+,\s*a0,\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a0,\s*a1 +** add\s+[atx][0-9]+,\s*a[01],\s*a[01] ** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 ** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 ** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+