diff mbox series

[v1,1/2] Match: Add int type fits check for form 1 of .SAT_SUB imm operand

Message ID 20240902055245.3244978-1-pan2.li@intel.com
State New
Headers show
Series [v1,1/2] Match: Add int type fits check for form 1 of .SAT_SUB imm operand | expand

Commit Message

Li, Pan2 Sept. 2, 2024, 5:52 a.m. UTC 
From: Pan Li <pan2.li@intel.com>

This patch would like to add strict check for imm operand of .SAT_SUB
matching.  We have no type checking for imm operand in previous, which
may result in unexpected IL to be catched by .SAT_SUB pattern.

We leverage the int_fits_type_p here to make sure the imm operand is
a int type fits the result type of the .SAT_SUB.  For example:

Fits uint8_t:
uint8_t a;
uint8_t sum = .SAT_SUB (12, a);
uint8_t sum = .SAT_SUB (12u, a);
uint8_t sum = .SAT_SUB (126u, a);
uint8_t sum = .SAT_SUB (128u, a);
uint8_t sum = .SAT_SUB (228, a);
uint8_t sum = .SAT_SUB (223u, a);

Not fits uint8_t:
uint8_t a;
uint8_t sum = .SAT_SUB (-1, a);
uint8_t sum = .SAT_SUB (256u, a);
uint8_t sum = .SAT_SUB (257, a);

The below test suite are passed for this patch:
* The rv64gcv fully regression test.
* The x86 bootstrap test.
* The x86 fully regression test.

gcc/ChangeLog:

	* match.pd: Add int_fits_type_p check for .SAT_SUB imm operand.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add test helper macros.
	* gcc.target/riscv/sat_u_add_imm_type_check-53.c: New test.
	* gcc.target/riscv/sat_u_add_imm_type_check-54.c: New test.
	* gcc.target/riscv/sat_u_add_imm_type_check-55.c: New test.
	* gcc.target/riscv/sat_u_add_imm_type_check-56.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/match.pd                                  |  2 +-
 gcc/testsuite/gcc.target/riscv/sat_arith.h    | 14 ++++++++++
 .../riscv/sat_u_add_imm_type_check-53.c       | 18 +++++++++++++
 .../riscv/sat_u_add_imm_type_check-54.c       | 27 +++++++++++++++++++
 .../riscv/sat_u_add_imm_type_check-55.c       | 18 +++++++++++++
 .../riscv/sat_u_add_imm_type_check-56.c       | 27 +++++++++++++++++++
 6 files changed, 105 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-53.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-54.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-55.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-56.c

Comments

Jeff Law Sept. 3, 2024, 1:47 p.m. UTC | #1 
On 9/1/24 11:52 PM, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
> 
> This patch would like to add strict check for imm operand of .SAT_SUB
> matching.  We have no type checking for imm operand in previous, which
> may result in unexpected IL to be catched by .SAT_SUB pattern.
> 
> We leverage the int_fits_type_p here to make sure the imm operand is
> a int type fits the result type of the .SAT_SUB.  For example:
> 
> Fits uint8_t:
> uint8_t a;
> uint8_t sum = .SAT_SUB (12, a);
> uint8_t sum = .SAT_SUB (12u, a);
> uint8_t sum = .SAT_SUB (126u, a);
> uint8_t sum = .SAT_SUB (128u, a);
> uint8_t sum = .SAT_SUB (228, a);
> uint8_t sum = .SAT_SUB (223u, a);
> 
> Not fits uint8_t:
> uint8_t a;
> uint8_t sum = .SAT_SUB (-1, a);
> uint8_t sum = .SAT_SUB (256u, a);
> uint8_t sum = .SAT_SUB (257, a);
> 
> The below test suite are passed for this patch:
> * The rv64gcv fully regression test.
> * The x86 bootstrap test.
> * The x86 fully regression test.
> 
> gcc/ChangeLog:
> 
> 	* match.pd: Add int_fits_type_p check for .SAT_SUB imm operand.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/sat_arith.h: Add test helper macros.
> 	* gcc.target/riscv/sat_u_add_imm_type_check-53.c: New test.
> 	* gcc.target/riscv/sat_u_add_imm_type_check-54.c: New test.
> 	* gcc.target/riscv/sat_u_add_imm_type_check-55.c: New test.
> 	* gcc.target/riscv/sat_u_add_imm_type_check-56.c: New test.
Testsuite bits are fine for both patches in this series.

match.pd bits are fine as well if nobody objects in 48hrs.

jeff
diff mbox series

Patch

diff --git a/gcc/match.pd b/gcc/match.pd
index be211535a49..45e0cc4a54f 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -3269,7 +3269,7 @@  DEFINE_INT_AND_FLOAT_ROUND_FN (RINT)
 (match (unsigned_integer_sat_sub @0 @1)
  (cond^ (le @1 INTEGER_CST@2) (minus INTEGER_CST@0 @1) integer_zerop)
  (if (INTEGRAL_TYPE_P (type) && TYPE_UNSIGNED (type)
-     && types_match (type, @1))
+     && types_match (type, @1) && int_fits_type_p (@0, type))
  (with
   {
    unsigned precision = TYPE_PRECISION (type);
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index a899979904b..75f48b4b760 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -267,6 +267,20 @@  sat_u_sub_imm##IMM##_##T##_fmt_4 (T x)  \
 #define RUN_SAT_U_SUB_IMM_FMT_4(T, x, IMM, expect) \
   if (sat_u_sub_imm##IMM##_##T##_fmt_4(x) != expect) __builtin_abort ()
 
+#define DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1(INDEX, T, IMM) \
+T __attribute__((noinline))                               \
+sat_u_sub_imm_type_check##_##INDEX##_##T##_fmt_1 (T y)    \
+{                                                         \
+  return IMM >= y ? IMM - y : 0;                          \
+}
+
+#define DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2(INDEX, T, IMM) \
+T __attribute__((noinline))                               \
+sat_u_sub_imm_type_check##_##INDEX##_##T##_fmt_2 (T y)    \
+{                                                         \
+  return IMM > y ? IMM - y : 0;                           \
+}
+
 /******************************************************************************/
 /* Saturation Truncate (unsigned and signed)                                  */
 /******************************************************************************/
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-53.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-53.c
new file mode 100644
index 00000000000..c959eeb0d86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-53.c
@@ -0,0 +1,18 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (0, uint8_t, -43)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (1, uint8_t, 269)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (2, uint8_t, 369u)
+
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (3, uint16_t, -4)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (4, uint16_t, 65579)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (5, uint16_t, 65679u)
+
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (6, uint32_t, -62)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (7, uint32_t, 4294967342ll)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (8, uint32_t, 4394967342ull)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-54.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-54.c
new file mode 100644
index 00000000000..abc19e22be4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-54.c
@@ -0,0 +1,27 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (0, uint8_t, 123u)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (1, uint8_t, 9)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (2, uint8_t, 129)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (3, uint8_t, 234u)
+
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (4, uint16_t, 32763u)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (5, uint16_t, 65532u)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (6, uint16_t, 52767)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (7, uint16_t, 9)
+
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (8,  uint32_t, 4294967293u)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (9,  uint32_t, 2147483944)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (10, uint32_t, 4294967242)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (11, uint32_t, 2147483644u)
+
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (12, uint64_t, -6232)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (13, uint64_t, 6293232)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (14, uint64_t, 576460752303483482)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (15, uint64_t, 576460752303423482u)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_1 (16, uint64_t, 976460752303483482u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 34 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-55.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-55.c
new file mode 100644
index 00000000000..e9c3fd51eb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-55.c
@@ -0,0 +1,18 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (0, uint8_t, -43)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (1, uint8_t, 269)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (2, uint8_t, 369u)
+
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (3, uint16_t, -4)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (4, uint16_t, 65579)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (5, uint16_t, 65679u)
+
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (6, uint32_t, -62)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (7, uint32_t, 4294967342ll)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (8, uint32_t, 4394967342ull)
+
+/* { dg-final { scan-rtl-dump-not ".SAT_ADD " "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-56.c b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-56.c
new file mode 100644
index 00000000000..3f8e3e1b7d3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_add_imm_type_check-56.c
@@ -0,0 +1,27 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (0, uint8_t, 126u)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (1, uint8_t, 9)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (2, uint8_t, 129)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (3, uint8_t, 254u)
+
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (4, uint16_t, 32767u)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (5, uint16_t, 65534u)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (6, uint16_t, 52767)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (7, uint16_t, 9)
+
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (8,  uint32_t, 4294967293u)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (9,  uint32_t, 2147483944)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (10, uint32_t, 4294967242)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (11, uint32_t, 2147483644u)
+
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (12, uint64_t, -6232)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (13, uint64_t, 6293232)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (14, uint64_t, 576460752303483482)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (15, uint64_t, 576460752303423482u)
+DEF_SAT_U_SUB_IMM_TYPE_CHECK_FMT_2 (16, uint64_t, 976460752303483482u)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 34 "expand" } } */