diff mbox series

[v1,1/2] RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM

Message ID 20240830030456.503727-1-pan2.li@intel.com
State New
Headers show
Series [v1,1/2] RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM | expand

Commit Message

Li, Pan2 Aug. 30, 2024, 3:04 a.m. UTC 
From: Pan Li <pan2.li@intel.com>

This patch would like to add test cases for the unsigned vector .SAT_ADD
when one of the operand is IMM.

Form 3:
  #define DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM)                          \
  T __attribute__((noinline))                                          \
  vec_sat_u_add_imm##IMM##_##T##_fmt_3 (T *out, T *in, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    T ret;                                                             \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        out[i] = __builtin_add_overflow (in[i], IMM, &ret) ? -1 : ret; \
      }                                                                \
  }

DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 123)

The below test are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-10.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-11.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-12.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-9.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 .../rvv/autovec/binop/vec_sat_u_add_imm-10.c  | 14 ++++++++++
 .../rvv/autovec/binop/vec_sat_u_add_imm-11.c  | 14 ++++++++++
 .../rvv/autovec/binop/vec_sat_u_add_imm-12.c  | 14 ++++++++++
 .../rvv/autovec/binop/vec_sat_u_add_imm-9.c   | 14 ++++++++++
 .../autovec/binop/vec_sat_u_add_imm-run-10.c  | 28 +++++++++++++++++++
 .../autovec/binop/vec_sat_u_add_imm-run-11.c  | 28 +++++++++++++++++++
 .../autovec/binop/vec_sat_u_add_imm-run-12.c  | 28 +++++++++++++++++++
 .../autovec/binop/vec_sat_u_add_imm-run-9.c   | 28 +++++++++++++++++++
 8 files changed, 168 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-9.c

Comments

Jeff Law Sept. 1, 2024, 3:19 p.m. UTC | #1 
On 8/29/24 9:04 PM, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
> 
> This patch would like to add test cases for the unsigned vector .SAT_ADD
> when one of the operand is IMM.
> 
> Form 3:
>    #define DEF_VEC_SAT_U_ADD_IMM_FMT_3(T, IMM)                          \
>    T __attribute__((noinline))                                          \
>    vec_sat_u_add_imm##IMM##_##T##_fmt_3 (T *out, T *in, unsigned limit) \
>    {                                                                    \
>      unsigned i;                                                        \
>      T ret;                                                             \
>      for (i = 0; i < limit; i++)                                        \
>        {                                                                \
>          out[i] = __builtin_add_overflow (in[i], IMM, &ret) ? -1 : ret; \
>        }                                                                \
>    }
> 
> DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 123)
> 
> The below test are passed for this patch.
> * The rv64gcv fully regression test.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c: New test.
> 	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c: New test.
> 	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c: New test.
> 	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c: New test.
> 	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-10.c: New test.
> 	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-11.c: New test.
> 	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-12.c: New test.
> 	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-9.c: New test.
Both patches in this series are OK.
jeff
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c
new file mode 100644
index 00000000000..b6b605ac615
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-10.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_add_imm15_uint16_t_fmt_3:
+** ...
+** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*15
+** ...
+*/
+DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint16_t, 15)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c
new file mode 100644
index 00000000000..6da86a1abe1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-11.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_add_imm33u_uint32_t_fmt_3:
+** ...
+** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** ...
+*/
+DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint32_t, 33u)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c
new file mode 100644
index 00000000000..b6ff5a6d5d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-12.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_add_imm129ull_uint64_t_fmt_3:
+** ...
+** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
+** ...
+*/
+DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint64_t, 129ull)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c
new file mode 100644
index 00000000000..15e0a0567d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-9.c
@@ -0,0 +1,14 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-skip-if "" { *-*-* } { "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "../vec_sat_arith.h"
+
+/*
+** vec_sat_u_add_imm9u_uint8_t_fmt_3:
+** ...
+** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*9
+** ...
+*/
+DEF_VEC_SAT_U_ADD_IMM_FMT_3(uint8_t, 9u)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-10.c
new file mode 100644
index 00000000000..a96fd757f15
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-10.c
@@ -0,0 +1,28 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint16_t
+#define RUN(T, out, in, expect, IMM, N) \
+  RUN_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T,     0u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T,     1u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 65534u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 65535u)
+
+int
+main ()
+{
+  T out[N];
+  T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm);
+
+  RUN (T, out, d[0][0], d[0][1],     0u, N);
+  RUN (T, out, d[1][0], d[1][1],     1u, N);
+  RUN (T, out, d[2][0], d[2][1], 65534u, N);
+  RUN (T, out, d[3][0], d[3][1], 65535u, N);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-11.c
new file mode 100644
index 00000000000..bdfe5e8f7d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-11.c
@@ -0,0 +1,28 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint32_t
+#define RUN(T, out, in, expect, IMM, N) \
+  RUN_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T,          0u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T,          1u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 4294967295u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 4294967294u)
+
+int
+main ()
+{
+  T out[N];
+  T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm);
+
+  RUN (T, out, d[0][0], d[0][1],          0u, N);
+  RUN (T, out, d[1][0], d[1][1],          1u, N);
+  RUN (T, out, d[2][0], d[2][1], 4294967294u, N);
+  RUN (T, out, d[3][0], d[3][1], 4294967295u, N);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-12.c
new file mode 100644
index 00000000000..bf89c358243
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-12.c
@@ -0,0 +1,28 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint64_t
+#define RUN(T, out, in, expect, IMM, N) \
+  RUN_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T,                    0ull)
+DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T,                    1ull)
+DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 18446744073709551614ull)
+DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 18446744073709551615ull)
+
+int
+main ()
+{
+  T out[N];
+  T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm);
+
+  RUN (T, out, d[0][0], d[0][1],                    0ull, N);
+  RUN (T, out, d[1][0], d[1][1],                    1ull, N);
+  RUN (T, out, d[2][0], d[2][1], 18446744073709551614ull, N);
+  RUN (T, out, d[3][0], d[3][1], 18446744073709551615ull, N);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-9.c
new file mode 100644
index 00000000000..e218779829a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-9.c
@@ -0,0 +1,28 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "../vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T uint8_t
+#define RUN(T, out, in, expect, IMM, N) \
+  RUN_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T,   0u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T,   1u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 254u)
+DEF_VEC_SAT_U_ADD_IMM_FMT_3_WRAP (T, 255u)
+
+int
+main ()
+{
+  T out[N];
+  T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm);
+
+  RUN (T, out, d[0][0], d[0][1],   0u, N);
+  RUN (T, out, d[1][0], d[1][1],   1u, N);
+  RUN (T, out, d[2][0], d[2][1], 254u, N);
+  RUN (T, out, d[3][0], d[3][1], 255u, N);
+
+  return 0;
+}