diff mbox series

[v2,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2

Message ID 20240829081217.3939502-1-pan2.li@intel.com
State New
Headers show
Series [v2,1/2] RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2 | expand

Commit Message

Li, Pan2 Aug. 29, 2024, 8:12 a.m. UTC 
From: Pan Li <pan2.li@intel.com>

This patch would like to add test cases for the unsigned scalar quad and
oct .SAT_TRUNC form 2.  Aka:

Form 2:
  #define DEF_SAT_U_TRUC_FMT_2(NT, WT)     \
  NT __attribute__((noinline))             \
  sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
  {                                        \
    WT max = (WT)(NT)-1;                   \
    return x > max ? (NT) max : (NT)x;     \
  }

QUAD:
DEF_SAT_U_TRUC_FMT_2 (uint16_t, uint64_t)
DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint32_t)

OCT:
DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint64_t)

The below test is passed for this patch.
* The rv64gcv regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_u_trunc-10.c: New test.
	* gcc.target/riscv/sat_u_trunc-11.c: New test.
	* gcc.target/riscv/sat_u_trunc-12.c: New test.
	* gcc.target/riscv/sat_u_trunc-run-10.c: New test.
	* gcc.target/riscv/sat_u_trunc-run-11.c: New test.
	* gcc.target/riscv/sat_u_trunc-run-12.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 .../gcc.target/riscv/sat_u_trunc-10.c         | 17 ++++++++++++++++
 .../gcc.target/riscv/sat_u_trunc-11.c         | 17 ++++++++++++++++
 .../gcc.target/riscv/sat_u_trunc-12.c         | 20 +++++++++++++++++++
 .../gcc.target/riscv/sat_u_trunc-run-10.c     | 16 +++++++++++++++
 .../gcc.target/riscv/sat_u_trunc-run-11.c     | 16 +++++++++++++++
 .../gcc.target/riscv/sat_u_trunc-run-12.c     | 16 +++++++++++++++
 6 files changed, 102 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-12.c

Comments

Jeff Law Sept. 1, 2024, 3:26 p.m. UTC | #1 
On 8/29/24 2:12 AM, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
> 
> This patch would like to add test cases for the unsigned scalar quad and
> oct .SAT_TRUNC form 2.  Aka:
> 
> Form 2:
>    #define DEF_SAT_U_TRUC_FMT_2(NT, WT)     \
>    NT __attribute__((noinline))             \
>    sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
>    {                                        \
>      WT max = (WT)(NT)-1;                   \
>      return x > max ? (NT) max : (NT)x;     \
>    }
> 
> QUAD:
> DEF_SAT_U_TRUC_FMT_2 (uint16_t, uint64_t)
> DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint32_t)
> 
> OCT:
> DEF_SAT_U_TRUC_FMT_2 (uint8_t, uint64_t)
> 
> The below test is passed for this patch.
> * The rv64gcv regression test.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/sat_u_trunc-10.c: New test.
> 	* gcc.target/riscv/sat_u_trunc-11.c: New test.
> 	* gcc.target/riscv/sat_u_trunc-12.c: New test.
> 	* gcc.target/riscv/sat_u_trunc-run-10.c: New test.
> 	* gcc.target/riscv/sat_u_trunc-run-11.c: New test.
> 	* gcc.target/riscv/sat_u_trunc-run-12.c: New test.
Both of the patches in this series are OK.
jeff
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-10.c
new file mode 100644
index 00000000000..5ea8e613901
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-10.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_trunc_uint32_t_to_uint8_t_fmt_2:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUNC_FMT_2(uint8_t, uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-11.c
new file mode 100644
index 00000000000..3b45e2af9ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-11.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_trunc_uint64_t_to_uint8_t_fmt_2:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUNC_FMT_2(uint8_t, uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-12.c
new file mode 100644
index 00000000000..7ea2c93a301
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-12.c
@@ -0,0 +1,20 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_trunc_uint64_t_to_uint16_t_fmt_2:
+** li\s+[atx][0-9]+,\s*65536
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_TRUNC_FMT_2(uint16_t, uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-10.c
new file mode 100644
index 00000000000..2281610f335
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-10.c
@@ -0,0 +1,16 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 uint8_t
+#define T2 uint32_t
+
+DEF_SAT_U_TRUNC_FMT_2_WRAP(T1, T2)
+
+#define DATA           TEST_UNARY_DATA_WRAP(T1, T2)
+#define T              TEST_UNARY_STRUCT_DECL(T1, T2)
+#define RUN_UNARY(x)   RUN_SAT_U_TRUNC_FMT_2_WRAP(T1, T2, x)
+
+#include "scalar_sat_unary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-11.c
new file mode 100644
index 00000000000..126c97c855a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-11.c
@@ -0,0 +1,16 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 uint8_t
+#define T2 uint64_t
+
+DEF_SAT_U_TRUNC_FMT_2_WRAP(T1, T2)
+
+#define DATA           TEST_UNARY_DATA_WRAP(T1, T2)
+#define T              TEST_UNARY_STRUCT_DECL(T1, T2)
+#define RUN_UNARY(x)   RUN_SAT_U_TRUNC_FMT_2_WRAP(T1, T2, x)
+
+#include "scalar_sat_unary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-12.c
new file mode 100644
index 00000000000..61ad79d506b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-12.c
@@ -0,0 +1,16 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 uint16_t
+#define T2 uint64_t
+
+DEF_SAT_U_TRUNC_FMT_2_WRAP(T1, T2)
+
+#define DATA           TEST_UNARY_DATA_WRAP(T1, T2)
+#define T              TEST_UNARY_STRUCT_DECL(T1, T2)
+#define RUN_UNARY(x)   RUN_SAT_U_TRUNC_FMT_2_WRAP(T1, T2, x)
+
+#include "scalar_sat_unary.h"