diff mbox series

[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3

Message ID 20240827071701.1301268-1-pan2.li@intel.com
State New
Headers show
Series [v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3 | expand

Commit Message

Li, Pan2 Aug. 27, 2024, 7:17 a.m. UTC 
From: Pan Li <pan2.li@intel.com>

This patch would like to add test cases for the unsigned scalar
.SAT_SUB IMM form 3.  Aka:

Form 3:
  #define DEF_SAT_U_SUB_IMM_FMT_3(T, IMM) \
  T __attribute__((noinline))             \
  sat_u_sub_imm##IMM##_##T##_fmt_3 (T y)  \
  {                                       \
    return (T)IMM > y ? (T)IMM - y : 0;   \
  }

DEF_SAT_U_SUB_IMM_FMT_3(uint64_t, 23)

The below test is passed for this patch.
* The rv64gcv regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add test helper macros.
	* gcc.target/riscv/sat_u_sub_imm-10.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-10_1.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-10_2.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-11.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-11_1.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-11_2.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-12.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-9.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-9_1.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-9_2.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-run-10.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-run-11.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-run-12.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-run-9.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h    |  9 +++
 .../gcc.target/riscv/sat_u_sub_imm-10.c       | 21 +++++++
 .../gcc.target/riscv/sat_u_sub_imm-10_1.c     | 22 ++++++++
 .../gcc.target/riscv/sat_u_sub_imm-10_2.c     | 22 ++++++++
 .../gcc.target/riscv/sat_u_sub_imm-11.c       | 20 +++++++
 .../gcc.target/riscv/sat_u_sub_imm-11_1.c     | 22 ++++++++
 .../gcc.target/riscv/sat_u_sub_imm-11_2.c     | 22 ++++++++
 .../gcc.target/riscv/sat_u_sub_imm-12.c       | 19 +++++++
 .../gcc.target/riscv/sat_u_sub_imm-9.c        | 20 +++++++
 .../gcc.target/riscv/sat_u_sub_imm-9_1.c      | 20 +++++++
 .../gcc.target/riscv/sat_u_sub_imm-9_2.c      | 20 +++++++
 .../gcc.target/riscv/sat_u_sub_imm-run-10.c   | 56 +++++++++++++++++++
 .../gcc.target/riscv/sat_u_sub_imm-run-11.c   | 55 ++++++++++++++++++
 .../gcc.target/riscv/sat_u_sub_imm-run-12.c   | 48 ++++++++++++++++
 .../gcc.target/riscv/sat_u_sub_imm-run-9.c    | 56 +++++++++++++++++++
 15 files changed, 432 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-10_1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-10_2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-11_1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-11_2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-9.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-9_1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-9_2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-9.c

Comments

Jeff Law Aug. 27, 2024, 1:01 p.m. UTC | #1 
On 8/27/24 1:17 AM, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
> 
> This patch would like to add test cases for the unsigned scalar
> .SAT_SUB IMM form 3.  Aka:
> 
> Form 3:
>    #define DEF_SAT_U_SUB_IMM_FMT_3(T, IMM) \
>    T __attribute__((noinline))             \
>    sat_u_sub_imm##IMM##_##T##_fmt_3 (T y)  \
>    {                                       \
>      return (T)IMM > y ? (T)IMM - y : 0;   \
>    }
> 
> DEF_SAT_U_SUB_IMM_FMT_3(uint64_t, 23)
> 
> The below test is passed for this patch.
> * The rv64gcv regression test.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/sat_arith.h: Add test helper macros.
> 	* gcc.target/riscv/sat_u_sub_imm-10.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-10_1.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-10_2.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-11.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-11_1.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-11_2.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-12.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-9.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-9_1.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-9_2.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-run-10.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-run-11.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-run-12.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-run-9.c: New test.
Both patches in this series are OK.
jeff
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index c8ff8320d82..b4339eb0dff 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -231,6 +231,13 @@  sat_u_sub_imm##IMM##_##T##_fmt_2 (T x)  \
   return x >= (T)IMM ? x - (T)IMM : 0;  \
 }
 
+#define DEF_SAT_U_SUB_IMM_FMT_3(T, IMM) \
+T __attribute__((noinline))             \
+sat_u_sub_imm##IMM##_##T##_fmt_3 (T y)  \
+{                                       \
+  return (T)IMM > y ? (T)IMM - y : 0;   \
+}
+
 #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
 #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
 #define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -248,6 +255,8 @@  sat_u_sub_imm##IMM##_##T##_fmt_2 (T x)  \
   if (sat_u_sub_imm##IMM##_##T##_fmt_1(y) != expect) __builtin_abort ()
 #define RUN_SAT_U_SUB_IMM_FMT_2(T, x, IMM, expect) \
   if (sat_u_sub_imm##IMM##_##T##_fmt_2(x) != expect) __builtin_abort ()
+#define RUN_SAT_U_SUB_IMM_FMT_3(T, IMM, y, expect) \
+  if (sat_u_sub_imm##IMM##_##T##_fmt_3(y) != expect) __builtin_abort ()
 
 /******************************************************************************/
 /* Saturation Truncate (unsigned and signed)                                  */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-10.c
new file mode 100644
index 00000000000..db450d7cfbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-10.c
@@ -0,0 +1,21 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm6_uint16_t_fmt_3:
+** li\s+[atx][0-9]+,\s*6
+** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_3(uint16_t, 6)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-10_1.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-10_1.c
new file mode 100644
index 00000000000..fa7d689851e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-10_1.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm32769_uint16_t_fmt_3:
+** li\s+[atx][0-9]+,\s*32768
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
+** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_3(uint16_t, 32769)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-10_2.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-10_2.c
new file mode 100644
index 00000000000..6c611712491
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-10_2.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm65533_uint16_t_fmt_3:
+** li\s+[atx][0-9]+,\s*65536
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-3
+** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_3(uint16_t, 65533)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-11.c
new file mode 100644
index 00000000000..992a67ca330
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-11.c
@@ -0,0 +1,20 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm255_uint32_t_fmt_3:
+** li\s+[atx][0-9]+,\s*255
+** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** sext\.w\s+a0,\s*a0
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_3(uint32_t, 255)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-11_1.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-11_1.c
new file mode 100644
index 00000000000..ab7673afdc7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-11_1.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm2147483649_uint32_t_fmt_3:
+** li\s+[atx][0-9]+,\s*1
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
+** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** sext\.w\s+a0,\s*a0
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_3(uint32_t, 2147483649)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-11_2.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-11_2.c
new file mode 100644
index 00000000000..12d9968b715
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-11_2.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm68719476732_uint32_t_fmt_3:
+** li\s+[atx][0-9]+,\s*1
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-4
+** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** sext\.w\s+a0,\s*a0
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_3(uint32_t, 68719476732)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-12.c
new file mode 100644
index 00000000000..f8d49c7a61e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-12.c
@@ -0,0 +1,19 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm82_uint64_t_fmt_3:
+** li\s+[atx][0-9]+,\s*82
+** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_3(uint64_t, 82)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-9.c
new file mode 100644
index 00000000000..cdbc285fb3c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-9.c
@@ -0,0 +1,20 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm11_uint8_t_fmt_3:
+** li\s+[atx][0-9]+,\s*11
+** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_3(uint8_t, 11)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-9_1.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-9_1.c
new file mode 100644
index 00000000000..12a0fc669b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-9_1.c
@@ -0,0 +1,20 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm134_uint8_t_fmt_3:
+** li\s+[atx][0-9]+,\s*134
+** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_3(uint8_t, 134)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-9_2.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-9_2.c
new file mode 100644
index 00000000000..05ea9743665
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-9_2.c
@@ -0,0 +1,20 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm253_uint8_t_fmt_3:
+** li\s+[atx][0-9]+,\s*253
+** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_3(uint8_t, 253)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-10.c
new file mode 100644
index 00000000000..150ab2a490d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-10.c
@@ -0,0 +1,56 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_SUB_IMM_FMT_3(uint16_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_3(uint16_t, 1)
+DEF_SAT_U_SUB_IMM_FMT_3(uint16_t, 5)
+DEF_SAT_U_SUB_IMM_FMT_3(uint16_t, 32767)
+DEF_SAT_U_SUB_IMM_FMT_3(uint16_t, 32768)
+DEF_SAT_U_SUB_IMM_FMT_3(uint16_t, 65534)
+DEF_SAT_U_SUB_IMM_FMT_3(uint16_t, 65535)
+
+#define T                       uint16_t
+#define RUN(T, imm, op, expect) RUN_SAT_U_SUB_IMM_FMT_3(T, imm, op, expect)
+
+T d[][3] = {
+  /* arg_0, arg_1, expect */
+  {        0,     0,      0, },
+  {        1,     0,      1, },
+  {        1, 65535,      0, },
+  {    65534, 65534,      0, },
+  {    65534, 65535,      0, },
+  {    65534,     2,  65532, },
+  {    65535, 65534,      1, },
+  {    65535,     0,  65535, },
+  {        5,     2,      3, },
+  {        5,     6,      0, },
+  {    32767,     0,  32767, },
+  {    32768, 32767,      1, },
+};
+
+int
+main ()
+{
+  RUN (T,     0,  d[0][1],  d[0][2]);
+
+  RUN (T,     1,  d[1][1],  d[1][2]);
+  RUN (T,     1,  d[2][1],  d[2][2]);
+
+  RUN (T, 65534,  d[3][1],  d[3][2]);
+  RUN (T, 65534,  d[4][1],  d[4][2]);
+  RUN (T, 65534,  d[5][1],  d[5][2]);
+
+  RUN (T, 65535,  d[6][1],  d[6][2]);
+  RUN (T, 65535,  d[7][1],  d[7][2]);
+
+  RUN (T,     5,  d[8][1],  d[8][2]);
+  RUN (T,     5,  d[9][1],  d[9][2]);
+
+  RUN (T, 32767, d[10][1], d[10][2]);
+
+  RUN (T, 32768, d[11][1], d[11][2]);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-11.c
new file mode 100644
index 00000000000..c7d2850c0be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-11.c
@@ -0,0 +1,55 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_SUB_IMM_FMT_3(uint32_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_3(uint32_t, 1)
+DEF_SAT_U_SUB_IMM_FMT_3(uint32_t, 5)
+DEF_SAT_U_SUB_IMM_FMT_3(uint32_t, 2147483647)
+DEF_SAT_U_SUB_IMM_FMT_3(uint32_t, 2147483648)
+DEF_SAT_U_SUB_IMM_FMT_3(uint32_t, 4294967294)
+DEF_SAT_U_SUB_IMM_FMT_3(uint32_t, 4294967295)
+
+#define T                       uint32_t
+#define RUN(T, imm, op, expect) RUN_SAT_U_SUB_IMM_FMT_3(T, imm, op, expect)
+
+T d[][3] = {
+  /* arg_0, arg_1, expect */
+  {          0,          0,          0, },
+  {          1,          0,          1, },
+  {          1, 4294967295,          0, },
+  { 4294967294, 4294967294,          0, },
+  { 4294967294, 4294967295,          0, },
+  { 4294967294,          2, 4294967292, },
+  { 4294967295, 4294967294,          1, },
+  { 4294967295,          0, 4294967295, },
+  {          5,          2,          3, },
+  {          5,          6,          0, },
+  { 2147483647,          0, 2147483647, },
+  { 2147483648, 2147483647,          1, },
+};
+
+int
+main ()
+{
+  RUN (T,          0,  d[0][1],  d[0][2]);
+
+  RUN (T,          1,  d[1][1],  d[1][2]);
+  RUN (T,          1,  d[2][1],  d[2][2]);
+
+  RUN (T, 4294967294,  d[3][1],  d[3][2]);
+  RUN (T, 4294967294,  d[4][1],  d[4][2]);
+  RUN (T, 4294967294,  d[5][1],  d[5][2]);
+
+  RUN (T, 4294967295,  d[6][1],  d[6][2]);
+  RUN (T, 4294967295,  d[7][1],  d[7][2]);
+
+  RUN (T,          5,  d[8][1],  d[8][2]);
+  RUN (T,          5,  d[9][1],  d[9][2]);
+
+  RUN (T, 2147483647, d[10][1], d[10][2]);
+  RUN (T, 2147483648, d[11][1], d[11][2]);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-12.c
new file mode 100644
index 00000000000..6bf5cd2445a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-12.c
@@ -0,0 +1,48 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_SUB_IMM_FMT_3(uint64_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_3(uint64_t, 1)
+DEF_SAT_U_SUB_IMM_FMT_3(uint64_t, 5)
+DEF_SAT_U_SUB_IMM_FMT_3(uint64_t, 18446744073709551614u)
+DEF_SAT_U_SUB_IMM_FMT_3(uint64_t, 18446744073709551615u)
+
+#define T                       uint64_t
+#define RUN(T, imm, op, expect) RUN_SAT_U_SUB_IMM_FMT_3(T, imm, op, expect)
+
+T d[][3] = {
+  /* arg_0, arg_1, expect */
+  {                     0,                     0,                     0, },
+  {                     1,                     0,                     1, },
+  {                     1, 18446744073709551615u,                     0, },
+  { 18446744073709551614u, 18446744073709551614u,                     0, },
+  { 18446744073709551614u, 18446744073709551615u,                     0, },
+  { 18446744073709551614u,                     2, 18446744073709551612u, },
+  { 18446744073709551615u, 18446744073709551614u,                     1, },
+  { 18446744073709551615u,                     0, 18446744073709551615u, },
+  {                     5,                     2,                     3, },
+  {                     5,                     6,                     0, },
+};
+
+int
+main ()
+{
+  RUN (T,                     0, d[0][1], d[0][2]);
+
+  RUN (T,                     1, d[1][1], d[1][2]);
+  RUN (T,                     1, d[2][1], d[2][2]);
+
+  RUN (T, 18446744073709551614u, d[3][1], d[3][2]);
+  RUN (T, 18446744073709551614u, d[4][1], d[4][2]);
+  RUN (T, 18446744073709551614u, d[5][1], d[5][2]);
+
+  RUN (T, 18446744073709551615u, d[6][1], d[6][2]);
+  RUN (T, 18446744073709551615u, d[7][1], d[7][2]);
+
+  RUN (T,                     5, d[8][1], d[8][2]);
+  RUN (T,                     5, d[9][1], d[9][2]);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-9.c
new file mode 100644
index 00000000000..dfef1f24a9e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-9.c
@@ -0,0 +1,56 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_SUB_IMM_FMT_3(uint8_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_3(uint8_t, 1)
+DEF_SAT_U_SUB_IMM_FMT_3(uint8_t, 5)
+DEF_SAT_U_SUB_IMM_FMT_3(uint8_t, 127)
+DEF_SAT_U_SUB_IMM_FMT_3(uint8_t, 128)
+DEF_SAT_U_SUB_IMM_FMT_3(uint8_t, 254)
+DEF_SAT_U_SUB_IMM_FMT_3(uint8_t, 255)
+
+#define T                       uint8_t
+#define RUN(T, imm, op, expect) RUN_SAT_U_SUB_IMM_FMT_3(T, imm, op, expect)
+
+T d[][3] = {
+  /* arg_0, arg_1, expect */
+  {      0,     0,      0, },
+  {      1,     0,      1, },
+  {      1,   255,      0, },
+  {    254,   254,      0, },
+  {    254,   255,      0, },
+  {    254,     2,    252, },
+  {    255,   254,      1, },
+  {    255,     0,    255, },
+  {      5,     2,      3, },
+  {      5,     6,      0, },
+  {    127,     0,    127, },
+  {    128,   129,      0, },
+};
+
+int
+main ()
+{
+  RUN (T,   0,  d[0][1],  d[0][2]);
+
+  RUN (T,   1,  d[1][1],  d[1][2]);
+  RUN (T,   1,  d[2][1],  d[2][2]);
+
+  RUN (T, 254,  d[3][1],  d[3][2]);
+  RUN (T, 254,  d[4][1],  d[4][2]);
+  RUN (T, 254,  d[5][1],  d[5][2]);
+
+  RUN (T, 255,  d[6][1],  d[6][2]);
+  RUN (T, 255,  d[7][1],  d[7][2]);
+
+  RUN (T,   5,  d[8][1],  d[8][2]);
+  RUN (T,   5,  d[9][1],  d[9][2]);
+
+  RUN (T, 127, d[10][1], d[10][2]);
+
+  RUN (T, 128, d[11][1], d[11][2]);
+
+  return 0;
+}