diff mbox series

[v1] RISC-V: Support IMM for operand 1 of ussub pattern

Message ID 20240826102609.3718963-1-pan2.li@intel.com
State New
Headers show
Series [v1] RISC-V: Support IMM for operand 1 of ussub pattern | expand

Commit Message

Li, Pan2 Aug. 26, 2024, 10:26 a.m. UTC 
From: Pan Li <pan2.li@intel.com>

This patch would like to allow IMM for the operand 1 of ussub pattern.
Aka .SAT_SUB(x, 22) as the below example.

Form 2:
  #define DEF_SAT_U_SUB_IMM_FMT_2(T, IMM) \
  T __attribute__((noinline))             \
  sat_u_sub_imm##IMM##_##T##_fmt_2 (T x)  \
  {                                       \
    return x >= (T)IMM ? x - (T)IMM : 0;  \
  }

DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 1022)

It is almost the as support imm for operand 0 of ussub pattern, but
allow the second operand to be imm insted of the first operand.

The below test suites are passed for this patch:
1. The rv64gcv fully regression test.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_expand_ussub): Gen xmode for the
	second operand, aka y in parameter.
	* config/riscv/riscv.md (ussub<mode>3): Allow const_int for operand 2.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add test helper macros.
	* gcc.target/riscv/sat_u_sub_imm-5.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-5_1.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-5_2.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-6.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-6_1.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-6_2.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-7.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-7_1.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-7_2.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-8.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-run-5.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-run-6.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-run-7.c: New test.
	* gcc.target/riscv/sat_u_sub_imm-run-8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/riscv.cc                     |  2 +-
 gcc/config/riscv/riscv.md                     |  2 +-
 gcc/testsuite/gcc.target/riscv/sat_arith.h    |  9 +++
 .../gcc.target/riscv/sat_u_sub_imm-5.c        | 19 +++++++
 .../gcc.target/riscv/sat_u_sub_imm-5_1.c      | 19 +++++++
 .../gcc.target/riscv/sat_u_sub_imm-5_2.c      | 19 +++++++
 .../gcc.target/riscv/sat_u_sub_imm-6.c        | 20 +++++++
 .../gcc.target/riscv/sat_u_sub_imm-6_1.c      | 21 +++++++
 .../gcc.target/riscv/sat_u_sub_imm-6_2.c      | 22 ++++++++
 .../gcc.target/riscv/sat_u_sub_imm-7.c        | 19 +++++++
 .../gcc.target/riscv/sat_u_sub_imm-7_1.c      | 21 +++++++
 .../gcc.target/riscv/sat_u_sub_imm-7_2.c      | 22 ++++++++
 .../gcc.target/riscv/sat_u_sub_imm-8.c        | 18 ++++++
 .../gcc.target/riscv/sat_u_sub_imm-run-5.c    | 55 +++++++++++++++++++
 .../gcc.target/riscv/sat_u_sub_imm-run-6.c    | 55 +++++++++++++++++++
 .../gcc.target/riscv/sat_u_sub_imm-run-7.c    | 54 ++++++++++++++++++
 .../gcc.target/riscv/sat_u_sub_imm-run-8.c    | 48 ++++++++++++++++
 17 files changed, 423 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-8.c

Comments

Jeff Law Aug. 26, 2024, 1:54 p.m. UTC | #1 
On 8/26/24 4:26 AM, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
> 
> This patch would like to allow IMM for the operand 1 of ussub pattern.
> Aka .SAT_SUB(x, 22) as the below example.
> 
> Form 2:
>    #define DEF_SAT_U_SUB_IMM_FMT_2(T, IMM) \
>    T __attribute__((noinline))             \
>    sat_u_sub_imm##IMM##_##T##_fmt_2 (T x)  \
>    {                                       \
>      return x >= (T)IMM ? x - (T)IMM : 0;  \
>    }
> 
> DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 1022)
> 
> It is almost the as support imm for operand 0 of ussub pattern, but
> allow the second operand to be imm insted of the first operand.
> 
> The below test suites are passed for this patch:
> 1. The rv64gcv fully regression test.
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv.cc (riscv_expand_ussub): Gen xmode for the
> 	second operand, aka y in parameter.
> 	* config/riscv/riscv.md (ussub<mode>3): Allow const_int for operand 2.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/sat_arith.h: Add test helper macros.
> 	* gcc.target/riscv/sat_u_sub_imm-5.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-5_1.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-5_2.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-6.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-6_1.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-6_2.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-7.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-7_1.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-7_2.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-8.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-run-5.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-run-6.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-run-7.c: New test.
> 	* gcc.target/riscv/sat_u_sub_imm-run-8.c: New test.
OK
jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 90a6e936558..1f544c1287e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -11965,7 +11965,7 @@  riscv_expand_ussub (rtx dest, rtx x, rtx y)
 {
   machine_mode mode = GET_MODE (dest);
   rtx xmode_x = riscv_gen_unsigned_xmode_reg (x, mode);
-  rtx xmode_y = gen_lowpart (Xmode, y);
+  rtx xmode_y = riscv_gen_unsigned_xmode_reg (y, mode);
   rtx xmode_lt = gen_reg_rtx (Xmode);
   rtx xmode_minus = gen_reg_rtx (Xmode);
   rtx xmode_dest = gen_reg_rtx (Xmode);
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index a94705a8e7c..3289ed2155a 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -4370,7 +4370,7 @@  (define_expand "usadd<mode>3"
 (define_expand "ussub<mode>3"
   [(match_operand:ANYI 0 "register_operand")
    (match_operand:ANYI 1 "reg_or_int_operand")
-   (match_operand:ANYI 2 "register_operand")]
+   (match_operand:ANYI 2 "reg_or_int_operand")]
   ""
   {
     riscv_expand_ussub (operands[0], operands[1], operands[2]);
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index d3f7b5836c7..b05d973c4c6 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -208,6 +208,13 @@  sat_u_sub_imm##IMM##_##T##_fmt_1 (T y)  \
   return (T)IMM >= y ? (T)IMM - y : 0;  \
 }
 
+#define DEF_SAT_U_SUB_IMM_FMT_2(T, IMM) \
+T __attribute__((noinline))             \
+sat_u_sub_imm##IMM##_##T##_fmt_2 (T x)  \
+{                                       \
+  return x >= (T)IMM ? x - (T)IMM : 0;  \
+}
+
 #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
 #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
 #define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -223,6 +230,8 @@  sat_u_sub_imm##IMM##_##T##_fmt_1 (T y)  \
 
 #define RUN_SAT_U_SUB_IMM_FMT_1(T, IMM, y, expect) \
   if (sat_u_sub_imm##IMM##_##T##_fmt_1(y) != expect) __builtin_abort ()
+#define RUN_SAT_U_SUB_IMM_FMT_2(T, x, IMM, expect) \
+  if (sat_u_sub_imm##IMM##_##T##_fmt_2(x) != expect) __builtin_abort ()
 
 /******************************************************************************/
 /* Saturation Truncate (unsigned and signed)                                  */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5.c
new file mode 100644
index 00000000000..ed47bef8d5d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5.c
@@ -0,0 +1,19 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm11_uint8_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*a0,\s*-11
+** sltiu\s+a0,\s*[atx][0-9]+,\s*11
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 11)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_1.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_1.c
new file mode 100644
index 00000000000..39229b8c7c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_1.c
@@ -0,0 +1,19 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm128_uint8_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*a0,\s*-128
+** sltiu\s+a0,\s*[atx][0-9]+,\s*128
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 128)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_2.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_2.c
new file mode 100644
index 00000000000..25ad0931770
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-5_2.c
@@ -0,0 +1,19 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm253_uint8_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*a0,\s*-253
+** sltiu\s+a0,\s*[atx][0-9]+,\s*253
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 253)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6.c
new file mode 100644
index 00000000000..fa3e013b77f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6.c
@@ -0,0 +1,20 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm6_uint16_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*a0,\s*-6
+** sltiu\s+a0,\s*[atx][0-9]+,\s*6
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 6)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_1.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_1.c
new file mode 100644
index 00000000000..da41896f1f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_1.c
@@ -0,0 +1,21 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm32768_uint16_t_fmt_2:
+** li\s+[atx][0-9]+,\s*32768
+** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 32768)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_2.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_2.c
new file mode 100644
index 00000000000..e42e6e11651
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-6_2.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm65533_uint16_t_fmt_2:
+** li\s+[atx][0-9]+,\s*65536
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-3
+** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 65533)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7.c
new file mode 100644
index 00000000000..e45153a368c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7.c
@@ -0,0 +1,19 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm255_uint32_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*a0,\s*-255
+** sltiu\s+a0,\s*[atx][0-9]+,\s*255
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** sext\.w\s+a0,\s*a0
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 255)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_1.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_1.c
new file mode 100644
index 00000000000..c6b8e5ba3d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_1.c
@@ -0,0 +1,21 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm2147483648_uint32_t_fmt_2:
+** li\s+[atx][0-9]+,\s*1
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31
+** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** sext\.w\s+a0,\s*a0
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 2147483648)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_2.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_2.c
new file mode 100644
index 00000000000..d3f94a10cf9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-7_2.c
@@ -0,0 +1,22 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm68719476732_uint32_t_fmt_2:
+** li\s+[atx][0-9]+,\s*1
+** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-4
+** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** sext\.w\s+a0,\s*a0
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 68719476732)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-8.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-8.c
new file mode 100644
index 00000000000..898349d4f66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-8.c
@@ -0,0 +1,18 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_imm82_uint64_t_fmt_2:
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-82
+** sltiu\s+a0,\s*[atx][0-9]+,\s*82
+** addi\s+a0,\s*a0,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** ret
+*/
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 82)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-5.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-5.c
new file mode 100644
index 00000000000..627e81bca4b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-5.c
@@ -0,0 +1,55 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 2)
+DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 6)
+DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 129)
+DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 254)
+DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 255)
+
+#define T                       uint8_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_SUB_IMM_FMT_2(T, op, imm, expect)
+
+T d[][3] = {
+  /* arg_0, arg_1, expect */
+  {      0,     0,      0, },
+  {      1,     0,      1, },
+  {      1,   255,      0, },
+  {    254,   254,      0, },
+  {    254,   255,      0, },
+  {    254,     2,    252, },
+  {    255,   254,      1, },
+  {    255,     0,    255, },
+  {      5,     2,      3, },
+  {      5,     6,      0, },
+  {    127,     0,    127, },
+  {    128,   129,      0, },
+};
+
+int
+main ()
+{
+  RUN (T,  d[0][0],   0,  d[0][2]);
+
+  RUN (T,  d[1][0],   0,  d[1][2]);
+  RUN (T,  d[2][0], 255,  d[2][2]);
+
+  RUN (T,  d[3][0], 254,  d[3][2]);
+  RUN (T,  d[4][0], 255,  d[4][2]);
+  RUN (T,  d[5][0],   2,  d[5][2]);
+
+  RUN (T,  d[6][0], 254,  d[6][2]);
+  RUN (T,  d[7][0],   0,  d[7][2]);
+
+  RUN (T,  d[8][0],   2,  d[8][2]);
+  RUN (T,  d[9][0],   6,  d[9][2]);
+
+  RUN (T, d[10][0],   0, d[10][2]);
+
+  RUN (T, d[11][0], 129, d[11][2]);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-6.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-6.c
new file mode 100644
index 00000000000..8deed2bf28f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-6.c
@@ -0,0 +1,55 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 2)
+DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 6)
+DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 32767)
+DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 65534)
+DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 65535)
+
+#define T                       uint16_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_SUB_IMM_FMT_2(T, op, imm, expect)
+
+T d[][3] = {
+  /* arg_0, arg_1, expect */
+  {        0,     0,      0, },
+  {        1,     0,      1, },
+  {        1, 65535,      0, },
+  {    65534, 65534,      0, },
+  {    65534, 65535,      0, },
+  {    65534,     2,  65532, },
+  {    65535, 65534,      1, },
+  {    65535,     0,  65535, },
+  {        5,     2,      3, },
+  {        5,     6,      0, },
+  {    32767,     0,  32767, },
+  {    32768, 32767,      1, },
+};
+
+int
+main ()
+{
+  RUN (T,  d[0][0],     0,  d[0][2]);
+
+  RUN (T,  d[1][0],     0,  d[1][2]);
+  RUN (T,  d[2][0], 65535,  d[2][2]);
+
+  RUN (T,  d[3][0], 65534,  d[3][2]);
+  RUN (T,  d[4][0], 65535,  d[4][2]);
+  RUN (T,  d[5][0],     2,  d[5][2]);
+
+  RUN (T,  d[6][0], 65534,  d[6][2]);
+  RUN (T,  d[7][0],     0,  d[7][2]);
+
+  RUN (T,  d[8][0],     2,  d[8][2]);
+  RUN (T,  d[9][0],     6,  d[9][2]);
+
+  RUN (T, d[10][0],     0, d[10][2]);
+
+  RUN (T, d[11][0], 32767, d[11][2]);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-7.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-7.c
new file mode 100644
index 00000000000..7a3d7b0176f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-7.c
@@ -0,0 +1,54 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 2)
+DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 6)
+DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 2147483647)
+DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 4294967294)
+DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 4294967295)
+
+#define T                       uint32_t
+#define RUN(T, op, imm, expect) RUN_SAT_U_SUB_IMM_FMT_2(T, op, imm, expect)
+
+T d[][3] = {
+  /* arg_0, arg_1, expect */
+  {          0,          0,          0, },
+  {          1,          0,          1, },
+  {          1, 4294967295,          0, },
+  { 4294967294, 4294967294,          0, },
+  { 4294967294, 4294967295,          0, },
+  { 4294967294,          2, 4294967292, },
+  { 4294967295, 4294967294,          1, },
+  { 4294967295,          0, 4294967295, },
+  {          5,          2,          3, },
+  {          5,          6,          0, },
+  { 2147483647,          0, 2147483647, },
+  { 2147483648, 2147483647,          1, },
+};
+
+int
+main ()
+{
+  RUN (T,  d[0][0],          0,  d[0][2]);
+
+  RUN (T,  d[1][0],          0,  d[1][2]);
+  RUN (T,  d[2][0], 4294967295,  d[2][2]);
+
+  RUN (T,  d[3][0], 4294967294,  d[3][2]);
+  RUN (T,  d[4][0], 4294967295,  d[4][2]);
+  RUN (T,  d[5][0],          2,  d[5][2]);
+
+  RUN (T,  d[6][0], 4294967294,  d[6][2]);
+  RUN (T,  d[7][0],          0,  d[7][2]);
+
+  RUN (T,  d[8][0],          2,  d[8][2]);
+  RUN (T,  d[9][0],          6,  d[9][2]);
+
+  RUN (T, d[10][0],          0, d[10][2]);
+  RUN (T, d[11][0], 2147483647, d[11][2]);
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-8.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-8.c
new file mode 100644
index 00000000000..3ed1c90f78f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub_imm-run-8.c
@@ -0,0 +1,48 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 0)
+DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 2)
+DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 6)
+DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 18446744073709551614u)
+DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 18446744073709551615u)
+
+#define T                       uint64_t
+#define RUN(T, imm, op, expect) RUN_SAT_U_SUB_IMM_FMT_2(T, imm, op, expect)
+
+T d[][3] = {
+  /* arg_0, arg_1, expect */
+  {                     0,                     0,                     0, },
+  {                     1,                     0,                     1, },
+  {                     1, 18446744073709551615u,                     0, },
+  { 18446744073709551614u, 18446744073709551614u,                     0, },
+  { 18446744073709551614u, 18446744073709551615u,                     0, },
+  { 18446744073709551614u,                     2, 18446744073709551612u, },
+  { 18446744073709551615u, 18446744073709551614u,                     1, },
+  { 18446744073709551615u,                     0, 18446744073709551615u, },
+  {                     5,                     2,                     3, },
+  {                     5,                     6,                     0, },
+};
+
+int
+main ()
+{
+  RUN (T, d[0][0],                     0, d[0][2]);
+
+  RUN (T, d[1][0],                     0, d[1][2]);
+  RUN (T, d[2][0], 18446744073709551615u, d[2][2]);
+
+  RUN (T, d[3][0], 18446744073709551614u, d[3][2]);
+  RUN (T, d[4][0], 18446744073709551615u, d[4][2]);
+  RUN (T, d[5][0],                     2, d[5][2]);
+
+  RUN (T, d[6][0], 18446744073709551614u, d[6][2]);
+  RUN (T, d[7][0],                     0, d[7][2]);
+
+  RUN (T, d[8][0],                     2, d[8][2]);
+  RUN (T, d[9][0],                     6, d[9][2]);
+
+  return 0;
+}