diff mbox series

[v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4

Message ID 20240825061835.1931708-1-pan2.li@intel.com
State New
Headers show
Series [v1,1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4 | expand

Commit Message

Li, Pan2 Aug. 25, 2024, 6:18 a.m. UTC 
From: Pan Li <pan2.li@intel.com>

This patch would like to add test cases for the unsigned scalar quad and
oct .SAT_TRUNC form 4.  Aka:

Form 4:
  #define DEF_SAT_U_TRUNC_FMT_4(NT, WT)          \
  NT __attribute__((noinline))                   \
  sat_u_trunc_##WT##_to_##NT##_fmt_4 (WT x)      \
  {                                              \
    bool not_overflow = x <= (WT)(NT)(-1);       \
    return ((NT)x) | (NT)((NT)not_overflow - 1); \
  }

The below test is passed for this patch.
* The rv64gcv regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add test helper macros.
	* gcc.target/riscv/sat_u_trunc-19.c: New test.
	* gcc.target/riscv/sat_u_trunc-20.c: New test.
	* gcc.target/riscv/sat_u_trunc-21.c: New test.
	* gcc.target/riscv/sat_u_trunc-22.c: New test.
	* gcc.target/riscv/sat_u_trunc-23.c: New test.
	* gcc.target/riscv/sat_u_trunc-24.c: New test.
	* gcc.target/riscv/sat_u_trunc-run-19.c: New test.
	* gcc.target/riscv/sat_u_trunc-run-20.c: New test.
	* gcc.target/riscv/sat_u_trunc-run-21.c: New test.
	* gcc.target/riscv/sat_u_trunc-run-22.c: New test.
	* gcc.target/riscv/sat_u_trunc-run-23.c: New test.
	* gcc.target/riscv/sat_u_trunc-run-24.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h    | 12 +++++++++++
 .../gcc.target/riscv/sat_u_trunc-19.c         | 17 ++++++++++++++++
 .../gcc.target/riscv/sat_u_trunc-20.c         | 20 +++++++++++++++++++
 .../gcc.target/riscv/sat_u_trunc-21.c         | 19 ++++++++++++++++++
 .../gcc.target/riscv/sat_u_trunc-22.c         | 17 ++++++++++++++++
 .../gcc.target/riscv/sat_u_trunc-23.c         | 17 ++++++++++++++++
 .../gcc.target/riscv/sat_u_trunc-24.c         | 20 +++++++++++++++++++
 .../gcc.target/riscv/sat_u_trunc-run-19.c     | 16 +++++++++++++++
 .../gcc.target/riscv/sat_u_trunc-run-20.c     | 16 +++++++++++++++
 .../gcc.target/riscv/sat_u_trunc-run-21.c     | 16 +++++++++++++++
 .../gcc.target/riscv/sat_u_trunc-run-22.c     | 16 +++++++++++++++
 .../gcc.target/riscv/sat_u_trunc-run-23.c     | 16 +++++++++++++++
 .../gcc.target/riscv/sat_u_trunc-run-24.c     | 16 +++++++++++++++
 13 files changed, 218 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-19.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-21.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-22.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-23.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-24.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-19.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-21.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-22.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-23.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-24.c

Comments

Jeff Law Aug. 25, 2024, 1:27 p.m. UTC | #1 
On 8/25/24 12:18 AM, pan2.li@intel.com wrote:
> From: Pan Li <pan2.li@intel.com>
> 
> This patch would like to add test cases for the unsigned scalar quad and
> oct .SAT_TRUNC form 4.  Aka:
> 
> Form 4:
>    #define DEF_SAT_U_TRUNC_FMT_4(NT, WT)          \
>    NT __attribute__((noinline))                   \
>    sat_u_trunc_##WT##_to_##NT##_fmt_4 (WT x)      \
>    {                                              \
>      bool not_overflow = x <= (WT)(NT)(-1);       \
>      return ((NT)x) | (NT)((NT)not_overflow - 1); \
>    }
> 
> The below test is passed for this patch.
> * The rv64gcv regression test.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/sat_arith.h: Add test helper macros.
> 	* gcc.target/riscv/sat_u_trunc-19.c: New test.
> 	* gcc.target/riscv/sat_u_trunc-20.c: New test.
> 	* gcc.target/riscv/sat_u_trunc-21.c: New test.
> 	* gcc.target/riscv/sat_u_trunc-22.c: New test.
> 	* gcc.target/riscv/sat_u_trunc-23.c: New test.
> 	* gcc.target/riscv/sat_u_trunc-24.c: New test.
> 	* gcc.target/riscv/sat_u_trunc-run-19.c: New test.
> 	* gcc.target/riscv/sat_u_trunc-run-20.c: New test.
> 	* gcc.target/riscv/sat_u_trunc-run-21.c: New test.
> 	* gcc.target/riscv/sat_u_trunc-run-22.c: New test.
> 	* gcc.target/riscv/sat_u_trunc-run-23.c: New test.
> 	* gcc.target/riscv/sat_u_trunc-run-24.c: New test.
Both patches in this series are fine.

Thanks,
jeff
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index 91853b60f59..229e1f0a5cd 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -245,6 +245,15 @@  sat_u_trunc_##WT##_to_##NT##_fmt_3 (WT x) \
 }
 #define DEF_SAT_U_TRUNC_FMT_3_WRAP(NT, WT) DEF_SAT_U_TRUNC_FMT_3(NT, WT)
 
+#define DEF_SAT_U_TRUNC_FMT_4(NT, WT)          \
+NT __attribute__((noinline))                   \
+sat_u_trunc_##WT##_to_##NT##_fmt_4 (WT x)      \
+{                                              \
+  bool not_overflow = x <= (WT)(NT)(-1);       \
+  return ((NT)x) | (NT)((NT)not_overflow - 1); \
+}
+#define DEF_SAT_U_TRUNC_FMT_4_WRAP(NT, WT) DEF_SAT_U_TRUNC_FMT_4(NT, WT)
+
 #define RUN_SAT_U_TRUNC_FMT_1(NT, WT, x) sat_u_trunc_##WT##_to_##NT##_fmt_1 (x)
 #define RUN_SAT_U_TRUNC_FMT_1_WRAP(NT, WT, x) RUN_SAT_U_TRUNC_FMT_1(NT, WT, x)
 
@@ -254,4 +263,7 @@  sat_u_trunc_##WT##_to_##NT##_fmt_3 (WT x) \
 #define RUN_SAT_U_TRUNC_FMT_3(NT, WT, x) sat_u_trunc_##WT##_to_##NT##_fmt_3 (x)
 #define RUN_SAT_U_TRUNC_FMT_3_WRAP(NT, WT, x) RUN_SAT_U_TRUNC_FMT_3(NT, WT, x)
 
+#define RUN_SAT_U_TRUNC_FMT_4(NT, WT, x) sat_u_trunc_##WT##_to_##NT##_fmt_4 (x)
+#define RUN_SAT_U_TRUNC_FMT_4_WRAP(NT, WT, x) RUN_SAT_U_TRUNC_FMT_4(NT, WT, x)
+
 #endif
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-19.c
new file mode 100644
index 00000000000..e61faffbbc6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-19.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_trunc_uint16_t_to_uint8_t_fmt_4:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUNC_FMT_4(uint8_t, uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-20.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-20.c
new file mode 100644
index 00000000000..708b2b2394d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-20.c
@@ -0,0 +1,20 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_trunc_uint32_t_to_uint16_t_fmt_4:
+** li\s+[atx][0-9]+,\s*65536
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_TRUNC_FMT_4(uint16_t, uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-21.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-21.c
new file mode 100644
index 00000000000..e522a90ecdb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-21.c
@@ -0,0 +1,19 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_trunc_uint64_t_to_uint32_t_fmt_4:
+** li\s+[atx][0-9]+,\s*-1
+** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32
+** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_TRUNC_FMT_4(uint32_t, uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-22.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-22.c
new file mode 100644
index 00000000000..db75cd0c6dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-22.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_trunc_uint32_t_to_uint8_t_fmt_4:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUNC_FMT_4(uint8_t, uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-23.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-23.c
new file mode 100644
index 00000000000..7acc6587304
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-23.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_trunc_uint64_t_to_uint8_t_fmt_4:
+** sltiu\s+[atx][0-9]+,\s*a0,\s*255
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
+** ret
+*/
+DEF_SAT_U_TRUNC_FMT_4(uint8_t, uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-24.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-24.c
new file mode 100644
index 00000000000..32952f5b283
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-24.c
@@ -0,0 +1,20 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_trunc_uint64_t_to_uint16_t_fmt_4:
+** li\s+[atx][0-9]+,\s*65536
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_TRUNC_FMT_4(uint16_t, uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-19.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-19.c
new file mode 100644
index 00000000000..7f52283fbeb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-19.c
@@ -0,0 +1,16 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 uint8_t
+#define T2 uint16_t
+
+DEF_SAT_U_TRUNC_FMT_4_WRAP(T1, T2)
+
+#define DATA           TEST_UNARY_DATA_WRAP(T1, T2)
+#define T              TEST_UNARY_STRUCT_DECL(T1, T2)
+#define RUN_UNARY(x)   RUN_SAT_U_TRUNC_FMT_4_WRAP(T1, T2, x)
+
+#include "scalar_sat_unary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-20.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-20.c
new file mode 100644
index 00000000000..ee13f0abb9b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-20.c
@@ -0,0 +1,16 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 uint16_t
+#define T2 uint32_t
+
+DEF_SAT_U_TRUNC_FMT_4_WRAP(T1, T2)
+
+#define DATA           TEST_UNARY_DATA_WRAP(T1, T2)
+#define T              TEST_UNARY_STRUCT_DECL(T1, T2)
+#define RUN_UNARY(x)   RUN_SAT_U_TRUNC_FMT_4_WRAP(T1, T2, x)
+
+#include "scalar_sat_unary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-21.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-21.c
new file mode 100644
index 00000000000..a1b8a5f19d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-21.c
@@ -0,0 +1,16 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 uint32_t
+#define T2 uint64_t
+
+DEF_SAT_U_TRUNC_FMT_4_WRAP(T1, T2)
+
+#define DATA           TEST_UNARY_DATA_WRAP(T1, T2)
+#define T              TEST_UNARY_STRUCT_DECL(T1, T2)
+#define RUN_UNARY(x)   RUN_SAT_U_TRUNC_FMT_4_WRAP(T1, T2, x)
+
+#include "scalar_sat_unary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-22.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-22.c
new file mode 100644
index 00000000000..f056bd42e91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-22.c
@@ -0,0 +1,16 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 uint8_t
+#define T2 uint32_t
+
+DEF_SAT_U_TRUNC_FMT_4_WRAP(T1, T2)
+
+#define DATA           TEST_UNARY_DATA_WRAP(T1, T2)
+#define T              TEST_UNARY_STRUCT_DECL(T1, T2)
+#define RUN_UNARY(x)   RUN_SAT_U_TRUNC_FMT_4_WRAP(T1, T2, x)
+
+#include "scalar_sat_unary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-23.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-23.c
new file mode 100644
index 00000000000..96c06ebcd12
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-23.c
@@ -0,0 +1,16 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 uint8_t
+#define T2 uint64_t
+
+DEF_SAT_U_TRUNC_FMT_4_WRAP(T1, T2)
+
+#define DATA           TEST_UNARY_DATA_WRAP(T1, T2)
+#define T              TEST_UNARY_STRUCT_DECL(T1, T2)
+#define RUN_UNARY(x)   RUN_SAT_U_TRUNC_FMT_4_WRAP(T1, T2, x)
+
+#include "scalar_sat_unary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-24.c b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-24.c
new file mode 100644
index 00000000000..1623e521fce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-24.c
@@ -0,0 +1,16 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+#include "sat_arith_data.h"
+
+#define T1 uint16_t
+#define T2 uint64_t
+
+DEF_SAT_U_TRUNC_FMT_4_WRAP(T1, T2)
+
+#define DATA           TEST_UNARY_DATA_WRAP(T1, T2)
+#define T              TEST_UNARY_STRUCT_DECL(T1, T2)
+#define RUN_UNARY(x)   RUN_SAT_U_TRUNC_FMT_4_WRAP(T1, T2, x)
+
+#include "scalar_sat_unary.h"