| Message ID | 20240718041913.1050890-1-pan2.li@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v1] Doc: Add Standard-Names ustrunc and sstrunc for integer modes | expand |
On Wed, Jul 17, 2024 at 9:20 PM <pan2.li@intel.com> wrote: > > From: Pan Li <pan2.li@intel.com> > > This patch would like to add the doc for the Standard-Names > ustrunc and sstrunc, include both the scalar and vector integer > modes. Thanks for doing this and this looks mostly good to me (can't approve it). > > gcc/ChangeLog: > > * doc/md.texi: Add Standard-Names ustrunc and sstrunc. > > Signed-off-by: Pan Li <pan2.li@intel.com> > --- > gcc/doc/md.texi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi > index 7f4335e0aac..f116dede906 100644 > --- a/gcc/doc/md.texi > +++ b/gcc/doc/md.texi > @@ -5543,6 +5543,18 @@ means of constraints requiring operands 1 and 0 to be the same location. > @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3} > Similar, for other arithmetic operations. > > +@cindex @code{ustrunc@var{m}@var{n}2} instruction pattern > +@item @samp{ustrunc@var{m}@var{n}2} > +Truncate the operand 1, and storing the result in operand 0. There will > +be saturation during the trunction. The result will be saturated to the > +maximal value of operand 0 type if there is overflow when truncation. The s/type/mode/ . > +operand 1 must have mode @var{n}, and the operand 0 must have mode @var{m}. > +Both the scalar and vector integer modes are allowed. I don't think you need the article `the` here. It reads wrong with it at least to me. > + > +@cindex @code{sstrunc@var{m}@var{n}2} instruction pattern > +@item @samp{sstrunc@var{m}@var{n}2} > +Similar but for signed. > + > @cindex @code{andc@var{m}3} instruction pattern > @item @samp{andc@var{m}3} > Like @code{and@var{m}3}, but it uses bitwise-complement of operand 2 > -- > 2.34.1 >
On Thu, Jul 18, 2024 at 7:35 AM Andrew Pinski <pinskia@gmail.com> wrote: > > On Wed, Jul 17, 2024 at 9:20 PM <pan2.li@intel.com> wrote: > > > > From: Pan Li <pan2.li@intel.com> > > > > This patch would like to add the doc for the Standard-Names > > ustrunc and sstrunc, include both the scalar and vector integer > > modes. > > Thanks for doing this and this looks mostly good to me (can't approve it). Too bad. OK with the changes Andrew requested. Thanks, Richard. > > > > > gcc/ChangeLog: > > > > * doc/md.texi: Add Standard-Names ustrunc and sstrunc. > > > > Signed-off-by: Pan Li <pan2.li@intel.com> > > --- > > gcc/doc/md.texi | 12 ++++++++++++ > > 1 file changed, 12 insertions(+) > > > > diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi > > index 7f4335e0aac..f116dede906 100644 > > --- a/gcc/doc/md.texi > > +++ b/gcc/doc/md.texi > > @@ -5543,6 +5543,18 @@ means of constraints requiring operands 1 and 0 to be the same location. > > @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3} > > Similar, for other arithmetic operations. > > > > +@cindex @code{ustrunc@var{m}@var{n}2} instruction pattern > > +@item @samp{ustrunc@var{m}@var{n}2} > > +Truncate the operand 1, and storing the result in operand 0. There will > > +be saturation during the trunction. The result will be saturated to the > > +maximal value of operand 0 type if there is overflow when truncation. The > s/type/mode/ . > > +operand 1 must have mode @var{n}, and the operand 0 must have mode @var{m}. > > +Both the scalar and vector integer modes are allowed. > I don't think you need the article `the` here. It reads wrong with it > at least to me. > > > + > > +@cindex @code{sstrunc@var{m}@var{n}2} instruction pattern > > +@item @samp{sstrunc@var{m}@var{n}2} > > +Similar but for signed. > > + > > @cindex @code{andc@var{m}3} instruction pattern > > @item @samp{andc@var{m}3} > > Like @code{and@var{m}3}, but it uses bitwise-complement of operand 2 > > -- > > 2.34.1 > >
Thanks Richard and Andrew, will commit v2 with that changes. https://gcc.gnu.org/pipermail/gcc-patches/2024-July/657617.html Pan -----Original Message----- From: Richard Biener <richard.guenther@gmail.com> Sent: Thursday, July 18, 2024 3:00 PM To: Andrew Pinski <pinskia@gmail.com> Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; kito.cheng@gmail.com; tamar.christina@arm.com; jeffreyalaw@gmail.com; rdapp.gcc@gmail.com Subject: Re: [PATCH v1] Doc: Add Standard-Names ustrunc and sstrunc for integer modes On Thu, Jul 18, 2024 at 7:35 AM Andrew Pinski <pinskia@gmail.com> wrote: > > On Wed, Jul 17, 2024 at 9:20 PM <pan2.li@intel.com> wrote: > > > > From: Pan Li <pan2.li@intel.com> > > > > This patch would like to add the doc for the Standard-Names > > ustrunc and sstrunc, include both the scalar and vector integer > > modes. > > Thanks for doing this and this looks mostly good to me (can't approve it). Too bad. OK with the changes Andrew requested. Thanks, Richard. > > > > > gcc/ChangeLog: > > > > * doc/md.texi: Add Standard-Names ustrunc and sstrunc. > > > > Signed-off-by: Pan Li <pan2.li@intel.com> > > --- > > gcc/doc/md.texi | 12 ++++++++++++ > > 1 file changed, 12 insertions(+) > > > > diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi > > index 7f4335e0aac..f116dede906 100644 > > --- a/gcc/doc/md.texi > > +++ b/gcc/doc/md.texi > > @@ -5543,6 +5543,18 @@ means of constraints requiring operands 1 and 0 to be the same location. > > @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3} > > Similar, for other arithmetic operations. > > > > +@cindex @code{ustrunc@var{m}@var{n}2} instruction pattern > > +@item @samp{ustrunc@var{m}@var{n}2} > > +Truncate the operand 1, and storing the result in operand 0. There will > > +be saturation during the trunction. The result will be saturated to the > > +maximal value of operand 0 type if there is overflow when truncation. The > s/type/mode/ . > > +operand 1 must have mode @var{n}, and the operand 0 must have mode @var{m}. > > +Both the scalar and vector integer modes are allowed. > I don't think you need the article `the` here. It reads wrong with it > at least to me. > > > + > > +@cindex @code{sstrunc@var{m}@var{n}2} instruction pattern > > +@item @samp{sstrunc@var{m}@var{n}2} > > +Similar but for signed. > > + > > @cindex @code{andc@var{m}3} instruction pattern > > @item @samp{andc@var{m}3} > > Like @code{and@var{m}3}, but it uses bitwise-complement of operand 2 > > -- > > 2.34.1 > >
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 7f4335e0aac..f116dede906 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -5543,6 +5543,18 @@ means of constraints requiring operands 1 and 0 to be the same location. @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3} Similar, for other arithmetic operations. +@cindex @code{ustrunc@var{m}@var{n}2} instruction pattern +@item @samp{ustrunc@var{m}@var{n}2} +Truncate the operand 1, and storing the result in operand 0. There will +be saturation during the trunction. The result will be saturated to the +maximal value of operand 0 type if there is overflow when truncation. The +operand 1 must have mode @var{n}, and the operand 0 must have mode @var{m}. +Both the scalar and vector integer modes are allowed. + +@cindex @code{sstrunc@var{m}@var{n}2} instruction pattern +@item @samp{sstrunc@var{m}@var{n}2} +Similar but for signed. + @cindex @code{andc@var{m}3} instruction pattern @item @samp{andc@var{m}3} Like @code{and@var{m}3}, but it uses bitwise-complement of operand 2