[v1,2/2] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 2

Message ID	20240708141557.2764170-2-pan2.li@intel.com
State	New
Headers	show Return-Path: <gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9733F3864812 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Pan Li <pan2.li@intel.com> Subject: [PATCH v1 2/2] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 2 Date: Mon, 8 Jul 2024 22:15:57 +0800 Message-Id: <20240708141557.2764170-2-pan2.li@intel.com> In-Reply-To: <20240708141557.2764170-1-pan2.li@intel.com> References: <20240708141557.2764170-1-pan2.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org
Series	[v1,1/2] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1 \| expand [v1,1/2] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 1 [v1,2/2] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 2

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h index 0e5e07a38b6..f08fa99d270 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h @@ -159,12 +159,29 @@ vec_sat_u_add_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \ #define DEF_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, IMM) \ DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM) +#define DEF_VEC_SAT_U_ADD_IMM_FMT_2(T, IMM) \ +T __attribute__((noinline)) \ +vec_sat_u_add_imm##IMM##_##T##_fmt_2 (T *out, T *in, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + out[i] = (T)(in[i] + IMM) < in[i] ? -1 : (in[i] + IMM); \ +} +#define DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP(T, IMM) \ + DEF_VEC_SAT_U_ADD_IMM_FMT_2(T, IMM) + #define RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N) \ vec_sat_u_add_imm##IMM##_##T##_fmt_1(out, op_1, N); \ VALIDATE_RESULT (out, expect, N) #define RUN_VEC_SAT_U_ADD_IMM_FMT_1_WRAP(T, out, op_1, expect, IMM, N) \ RUN_VEC_SAT_U_ADD_IMM_FMT_1(T, out, op_1, expect, IMM, N) +#define RUN_VEC_SAT_U_ADD_IMM_FMT_2(T, out, op_1, expect, IMM, N) \ + vec_sat_u_add_imm##IMM##_##T##_fmt_2(out, op_1, N); \ + VALIDATE_RESULT (out, expect, N) +#define RUN_VEC_SAT_U_ADD_IMM_FMT_2_WRAP(T, out, op_1, expect, IMM, N) \ + RUN_VEC_SAT_U_ADD_IMM_FMT_2(T, out, op_1, expect, IMM, N) + /******************************************************************************/ /* Saturation Sub (Unsigned and Signed) */ /******************************************************************************/ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c new file mode 100644 index 00000000000..d25fdcf78f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-5.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_add_imm9_uint8_t_fmt_2: +** ... +** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*9 +** ... +*/ +DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint8_t, 9) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c new file mode 100644 index 00000000000..e601f686a9d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-6.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_add_imm15_uint16_t_fmt_2: +** ... +** vsaddu\.vi\s+v[0-9]+,\s*v[0-9]+,\s*15 +** ... +*/ +DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint16_t, 15) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c new file mode 100644 index 00000000000..1d41a594b83 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_add_imm33_uint32_t_fmt_2: +** ... +** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint32_t, 33) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c new file mode 100644 index 00000000000..9ee356a28e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-8.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "vec_sat_arith.h" + +/* +** vec_sat_u_add_imm129_uint64_t_fmt_2: +** ... +** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** ... +*/ +DEF_VEC_SAT_U_ADD_IMM_FMT_2(uint64_t, 129) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-5.c new file mode 100644 index 00000000000..50037f5e4d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-5.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint8_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, 0) +DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, 1) +DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, 254) +DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, 255) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm); + + RUN (T, out, d[0][0], d[0][1], 0, N); + RUN (T, out, d[1][0], d[1][1], 1, N); + RUN (T, out, d[2][0], d[2][1], 254, N); + RUN (T, out, d[3][0], d[3][1], 255, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-6.c new file mode 100644 index 00000000000..9735a9ab144 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-6.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint16_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, 0) +DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, 1) +DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, 65534) +DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, 65535) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm); + + RUN (T, out, d[0][0], d[0][1], 0, N); + RUN (T, out, d[1][0], d[1][1], 1, N); + RUN (T, out, d[2][0], d[2][1], 65534, N); + RUN (T, out, d[3][0], d[3][1], 65535, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-7.c new file mode 100644 index 00000000000..44f4ef38d5a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-7.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint32_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, 0) +DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, 1) +DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, 4294967295) +DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, 4294967294) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm); + + RUN (T, out, d[0][0], d[0][1], 0, N); + RUN (T, out, d[1][0], d[1][1], 1, N); + RUN (T, out, d[2][0], d[2][1], 4294967294, N); + RUN (T, out, d[3][0], d[3][1], 4294967295, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-8.c new file mode 100644 index 00000000000..4309eb4851b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-run-8.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint64_t +#define RUN(T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, out, in, expect, IMM, N) + +DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, 0) +DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, 1) +DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, 18446744073709551614u) +DEF_VEC_SAT_U_ADD_IMM_FMT_2_WRAP (T, 18446744073709551615u) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_u_add_imm); + + RUN (T, out, d[0][0], d[0][1], 0, N); + RUN (T, out, d[1][0], d[1][1], 1, N); + RUN (T, out, d[2][0], d[2][1], 18446744073709551614u, N); + RUN (T, out, d[3][0], d[3][1], 18446744073709551615u, N); + + return 0; +}

[v1,2/2] RISC-V: Add testcases for unsigned vector .SAT_ADD IMM form 2

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