diff mbox series

[v1,1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3

Message ID 20240614021328.3032144-1-pan2.li@intel.com
State New
Headers show
Series [v1,1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3 | expand

Commit Message

Li, Pan2 June 14, 2024, 2:13 a.m. UTC
From: Pan Li <pan2.li@intel.com>

After the middle-end support the form 3 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 3 of unsigned .SAT_SUB.

Form 3:
  #define SAT_SUB_U_3(T) \
  T sat_sub_u_3_##T (T x, T y) \
  { \
    return x > y ? x - y : 0; \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add helper macro for test.
	* gcc.target/riscv/sat_u_sub-10.c: New test.
	* gcc.target/riscv/sat_u_sub-11.c: New test.
	* gcc.target/riscv/sat_u_sub-12.c: New test.
	* gcc.target/riscv/sat_u_sub-9.c: New test.
	* gcc.target/riscv/sat_u_sub-run-10.c: New test.
	* gcc.target/riscv/sat_u_sub-run-11.c: New test.
	* gcc.target/riscv/sat_u_sub-run-12.c: New test.
	* gcc.target/riscv/sat_u_sub-run-9.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/testsuite/gcc.target/riscv/sat_arith.h    |  8 ++++++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c | 19 ++++++++++++++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c | 18 +++++++++++++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c | 17 +++++++++++++
 gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c  | 18 +++++++++++++
 .../gcc.target/riscv/sat_u_sub-run-10.c       | 25 +++++++++++++++++++
 .../gcc.target/riscv/sat_u_sub-run-11.c       | 25 +++++++++++++++++++
 .../gcc.target/riscv/sat_u_sub-run-12.c       | 25 +++++++++++++++++++
 .../gcc.target/riscv/sat_u_sub-run-9.c        | 25 +++++++++++++++++++
 9 files changed, 180 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c

Comments

钟居哲 June 14, 2024, 2:24 a.m. UTC | #1
LGTM



juzhe.zhong@rivai.ai
 
From: pan2.li
Date: 2024-06-14 10:13
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3
From: Pan Li <pan2.li@intel.com>
 
After the middle-end support the form 3 of unsigned SAT_SUB and
the RISC-V backend implement the scalar .SAT_SUB, add more test
case to cover the form 3 of unsigned .SAT_SUB.
 
Form 3:
  #define SAT_SUB_U_3(T) \
  T sat_sub_u_3_##T (T x, T y) \
  { \
    return x > y ? x - y : 0; \
  }
 
Passed the rv64gcv fully regression test.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/sat_arith.h: Add helper macro for test.
* gcc.target/riscv/sat_u_sub-10.c: New test.
* gcc.target/riscv/sat_u_sub-11.c: New test.
* gcc.target/riscv/sat_u_sub-12.c: New test.
* gcc.target/riscv/sat_u_sub-9.c: New test.
* gcc.target/riscv/sat_u_sub-run-10.c: New test.
* gcc.target/riscv/sat_u_sub-run-11.c: New test.
* gcc.target/riscv/sat_u_sub-run-12.c: New test.
* gcc.target/riscv/sat_u_sub-run-9.c: New test.
 
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/testsuite/gcc.target/riscv/sat_arith.h    |  8 ++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c | 19 ++++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c | 18 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c | 17 +++++++++++++
gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c  | 18 +++++++++++++
.../gcc.target/riscv/sat_u_sub-run-10.c       | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-11.c       | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-12.c       | 25 +++++++++++++++++++
.../gcc.target/riscv/sat_u_sub-run-9.c        | 25 +++++++++++++++++++
9 files changed, 180 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c
 
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index bc9a372b6df..50c65cdea49 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -92,8 +92,16 @@ sat_u_sub_##T##_fmt_2 (T x, T y)  \
   return (x - y) & (-(T)(x > y)); \
}
+#define DEF_SAT_U_SUB_FMT_3(T)    \
+T __attribute__((noinline))       \
+sat_u_sub_##T##_fmt_3 (T x, T y)  \
+{                                 \
+  return x > y ? x - y : 0;       \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
+#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T)                                   \
void __attribute__((noinline))                                       \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
new file mode 100644
index 00000000000..6e78164865f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
new file mode 100644
index 00000000000..84e34657f55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
new file mode 100644
index 00000000000..eea282b21ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
new file mode 100644
index 00000000000..b24bf3eb549
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
new file mode 100644
index 00000000000..ea52ff4573e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T              uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+  /* arg_0, arg_1, expect */
+  {      0,     0,      0, },
+  {      0,     1,      0, },
+  {      1,     1,      0, },
+  {  65535, 65534,      1, },
+  {  65535, 65535,      0, },
+  {  65534, 65535,      0, },
+  {  65533, 65534,      0, },
+  {      0, 65535,      0, },
+  {      1, 65535,      0, },
+  {     35,     5,     30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
new file mode 100644
index 00000000000..fdea8916ab3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T              uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+  /*     arg_0,      arg_1,      expect */
+  {          0,          0,           0, },
+  {          0,          1,           0, },
+  {          1,          1,           0, },
+  { 4294967295, 4294967294,           1, },
+  { 4294967295, 4294967295,           0, },
+  { 4294967294, 4294967295,           0, },
+  { 4294967293, 4294967294,           0, },
+  {          1, 4294967295,           0, },
+  {          2, 4294967295,           0, },
+  {          5,          1,           4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
new file mode 100644
index 00000000000..164ee77fb76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T              uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+  /*                arg_0,                 arg_1,                 expect */
+  {                     0,                     0,                      0, },
+  {                     0,                     1,                      0, },
+  {                     1,                     1,                      0, },
+  { 18446744073709551615u, 18446744073709551614u,                      1, },
+  { 18446744073709551615u, 18446744073709551615u,                      0, },
+  { 18446744073709551614u, 18446744073709551615u,                      0, },
+  { 18446744073709551613u, 18446744073709551614u,                      0, },
+  {                     0, 18446744073709551615u,                      0, },
+  {                     1, 18446744073709551615u,                      0, },
+  {                    43,                    11,                     32, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c
new file mode 100644
index 00000000000..724adf92d3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T              uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+  /* arg_0, arg_1, expect */
+  {      0,     0,      0, },
+  {      0,     1,      0, },
+  {      1,     1,      0, },
+  {    255,   254,      1, },
+  {    255,   255,      0, },
+  {    254,   255,      0, },
+  {    253,   254,      0, },
+  {      0,   255,      0, },
+  {      1,   255,      0, },
+  {     32,     5,     27, },
+};
+
+#include "scalar_sat_binary.h"
Li, Pan2 June 14, 2024, 2:29 a.m. UTC | #2
Thanks Juzhe, will commit the series after the middle-end patch.

Pan

From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Friday, June 14, 2024 10:24 AM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Robin Dapp <rdapp.gcc@gmail.com>; Li, Pan2 <pan2.li@intel.com>
Subject: Re: [PATCH v1 1/8] RISC-V: Add testcases for scalar unsigned SAT_SUB form 3

LGTM
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index bc9a372b6df..50c65cdea49 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -92,8 +92,16 @@  sat_u_sub_##T##_fmt_2 (T x, T y)  \
   return (x - y) & (-(T)(x > y)); \
 }
 
+#define DEF_SAT_U_SUB_FMT_3(T)    \
+T __attribute__((noinline))       \
+sat_u_sub_##T##_fmt_3 (T x, T y)  \
+{                                 \
+  return x > y ? x - y : 0;       \
+}
+
 #define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
 #define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
+#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
 
 #define DEF_VEC_SAT_U_SUB_FMT_1(T)                                   \
 void __attribute__((noinline))                                       \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
new file mode 100644
index 00000000000..6e78164865f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-10.c
@@ -0,0 +1,19 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
new file mode 100644
index 00000000000..84e34657f55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-11.c
@@ -0,0 +1,18 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
new file mode 100644
index 00000000000..eea282b21ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-12.c
@@ -0,0 +1,17 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
new file mode 100644
index 00000000000..b24bf3eb549
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-9.c
@@ -0,0 +1,18 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_3:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_3(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
new file mode 100644
index 00000000000..ea52ff4573e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-10.c
@@ -0,0 +1,25 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T              uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+  /* arg_0, arg_1, expect */
+  {      0,     0,      0, },
+  {      0,     1,      0, },
+  {      1,     1,      0, },
+  {  65535, 65534,      1, },
+  {  65535, 65535,      0, },
+  {  65534, 65535,      0, },
+  {  65533, 65534,      0, },
+  {      0, 65535,      0, },
+  {      1, 65535,      0, },
+  {     35,     5,     30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
new file mode 100644
index 00000000000..fdea8916ab3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-11.c
@@ -0,0 +1,25 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T              uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+  /*     arg_0,      arg_1,      expect */
+  {          0,          0,           0, },
+  {          0,          1,           0, },
+  {          1,          1,           0, },
+  { 4294967295, 4294967294,           1, },
+  { 4294967295, 4294967295,           0, },
+  { 4294967294, 4294967295,           0, },
+  { 4294967293, 4294967294,           0, },
+  {          1, 4294967295,           0, },
+  {          2, 4294967295,           0, },
+  {          5,          1,           4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
new file mode 100644
index 00000000000..164ee77fb76
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-12.c
@@ -0,0 +1,25 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T              uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+  /*                arg_0,                 arg_1,                 expect */
+  {                     0,                     0,                      0, },
+  {                     0,                     1,                      0, },
+  {                     1,                     1,                      0, },
+  { 18446744073709551615u, 18446744073709551614u,                      1, },
+  { 18446744073709551615u, 18446744073709551615u,                      0, },
+  { 18446744073709551614u, 18446744073709551615u,                      0, },
+  { 18446744073709551613u, 18446744073709551614u,                      0, },
+  {                     0, 18446744073709551615u,                      0, },
+  {                     1, 18446744073709551615u,                      0, },
+  {                    43,                    11,                     32, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c
new file mode 100644
index 00000000000..724adf92d3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-9.c
@@ -0,0 +1,25 @@ 
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T              uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_3
+
+DEF_SAT_U_SUB_FMT_3(T)
+
+T test_data[][3] = {
+  /* arg_0, arg_1, expect */
+  {      0,     0,      0, },
+  {      0,     1,      0, },
+  {      1,     1,      0, },
+  {    255,   254,      1, },
+  {    255,   255,      0, },
+  {    254,   255,      0, },
+  {    253,   254,      0, },
+  {      0,   255,      0, },
+  {      1,   255,      0, },
+  {     32,     5,     27, },
+};
+
+#include "scalar_sat_binary.h"