[v2,2/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733]

Message ID	20240513184932.662109-3-vineetg@rivosinc.com
State	New
Headers	show Return-Path: <gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org> DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 04DEB38708EA From: Vineet Gupta <vineetg@rivosinc.com> To: gcc-patches@gcc.gnu.org Cc: Jeff Law <jeffreyalaw@gmail.com>, kito.cheng@gmail.com, Palmer Dabbelt <palmer@rivosinc.com>, =?utf-8?q?Christoph_M=C3=BCllner?= <christoph.muellner@vrull.eu>, Robin Dapp <rdapp.gcc@gmail.com>, gnu-toolchain@rivosinc.com, Vineet Gupta <vineetg@rivosinc.com> Subject: [PATCH v2 2/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733] Date: Mon, 13 May 2024 11:49:32 -0700 Message-Id: <20240513184932.662109-3-vineetg@rivosinc.com> In-Reply-To: <20240513184932.662109-1-vineetg@rivosinc.com> References: <20240513184932.662109-1-vineetg@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org
Series	RISC-V improve stack/array access by constant mat tweak \| expand [v2,0/2] RISC-V improve stack/array access by constant mat tweak [v2,1/2] RISC-V: avoid LUI based const materialization ... [part of PR/106265] [v2,2/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733]

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 706dc204e643..6da6ae4d041f 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -166,6 +166,8 @@ extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *); extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *); extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); extern bool riscv_reg_frame_related (rtx); +extern void riscv_split_sum_of_two_s12 (HOST_WIDE_INT, HOST_WIDE_INT *, + HOST_WIDE_INT *); /* Routines implemented in riscv-c.cc. */ void riscv_cpu_cpp_builtins (cpp_reader *); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 4067505270e1..4b742489b272 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4063,6 +4063,32 @@ riscv_split_doubleword_move (rtx dest, rtx src) riscv_emit_move (riscv_subword (dest, true), riscv_subword (src, true)); } } + +/* Constant VAL is known to be sum of two S12 constants. Break it into + comprising BASE and OFF. + Numerically S12 is -2048 to 2047, however it uses the more conservative + range -2048 to 2032 as offsets pertain to stack related registers. */ + +void +riscv_split_sum_of_two_s12 (HOST_WIDE_INT val, HOST_WIDE_INT *base, + HOST_WIDE_INT *off) +{ + if (SUM_OF_TWO_S12_N (val)) + { + *base = -2048; + *off = val - (-2048); + } + else if (SUM_OF_TWO_S12_P_ALGN (val)) + { + *base = 2032; + *off = val - 2032; + } + else + { + gcc_unreachable (); + } +} + /* Return the appropriate instructions to move SRC into DEST. Assume that SRC is operand 1 and DEST is operand 0. */ @@ -7852,6 +7878,17 @@ riscv_expand_prologue (void) GEN_INT (-constant_frame)); RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; } + else if (SUM_OF_TWO_S12_ALGN (-constant_frame)) + { + HOST_WIDE_INT base, off; + riscv_split_sum_of_two_s12 (-constant_frame, &base, &off); + insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, + GEN_INT (base)); + RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; + insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, + GEN_INT (off)); + RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; + } else { riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), GEN_INT (-constant_frame)); @@ -8074,14 +8111,26 @@ riscv_expand_epilogue (int style) } else { - if (!SMALL_OPERAND (adjust_offset.to_constant ())) + HOST_WIDE_INT adj_off_value = adjust_offset.to_constant (); + if (SMALL_OPERAND (adj_off_value)) + { + adjust = GEN_INT (adj_off_value); + } + else if (SUM_OF_TWO_S12_ALGN (adj_off_value)) + { + HOST_WIDE_INT base, off; + riscv_split_sum_of_two_s12 (adj_off_value, &base, &off); + insn = gen_add3_insn (stack_pointer_rtx, hard_frame_pointer_rtx, + GEN_INT (base)); + RTX_FRAME_RELATED_P (insn) = 1; + adjust = GEN_INT (off); + } + else { riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), - GEN_INT (adjust_offset.to_constant ())); + GEN_INT (adj_off_value)); adjust = RISCV_PROLOGUE_TEMP (Pmode); } - else - adjust = GEN_INT (adjust_offset.to_constant ()); } insn = emit_insn ( @@ -8148,10 +8197,21 @@ riscv_expand_epilogue (int style) /* Get an rtx for STEP1 that we can add to BASE. Skip if adjust equal to zero. */ - if (step1.to_constant () != 0) + HOST_WIDE_INT step1_value = step1.to_constant (); + if (step1_value != 0) { - rtx adjust = GEN_INT (step1.to_constant ()); - if (!SMALL_OPERAND (step1.to_constant ())) + rtx adjust = GEN_INT (step1_value); + if (SUM_OF_TWO_S12_ALGN (step1_value)) + { + HOST_WIDE_INT base, off; + riscv_split_sum_of_two_s12 (step1_value, &base, &off); + insn = emit_insn (gen_add3_insn (stack_pointer_rtx, + stack_pointer_rtx, + GEN_INT (base))); + RTX_FRAME_RELATED_P (insn) = 1; + adjust = GEN_INT (off); + } + else if (!SMALL_OPERAND (step1_value)) { riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust); adjust = RISCV_PROLOGUE_TEMP (Pmode); diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 0d27c0d378df..d6b14c4d6205 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -641,6 +641,13 @@ enum reg_class #define SUM_OF_TWO_S12(VALUE) \ (SUM_OF_TWO_S12_N (VALUE) || SUM_OF_TWO_S12_P (VALUE)) +/* Variant with first value 8 byte aligned if involving stack regs. */ +#define SUM_OF_TWO_S12_P_ALGN(VALUE) \ + (((VALUE) >= (2032 + 1)) && ((VALUE) <= (2032 * 2))) + +#define SUM_OF_TWO_S12_ALGN(VALUE) \ + (SUM_OF_TWO_S12_N (VALUE) || SUM_OF_TWO_S12_P_ALGN (VALUE)) + /* If this is a single bit mask, then we can load it with bseti. Special handling of SImode 0x80000000 on RV64 is done in riscv_build_integer_1. */ #define SINGLE_BIT_MASK_OPERAND(VALUE) \ diff --git a/gcc/testsuite/gcc.target/riscv/pr105733.c b/gcc/testsuite/gcc.target/riscv/pr105733.c new file mode 100644 index 000000000000..6156c36dc7ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr105733.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options { -march=rv64gcv -mabi=lp64d } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +#define BUF_SIZE 2064 + +void +foo(unsigned long i) +{ + volatile char buf[BUF_SIZE]; + + buf[i] = 0; +} + +/* { dg-final { scan-assembler-not {li\t[a-x0-9]+,4096} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c index b64c73f34f13..6afcf1db593b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-1.c @@ -129,5 +129,5 @@ spill_12 (int8_t *in, int8_t *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c index 8fcdca705384..544e8628a27b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-2.c @@ -120,5 +120,5 @@ spill_11 (int16_t *in, int16_t *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c index ca296ce02d66..4bfeb07e9aca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-3.c @@ -111,5 +111,5 @@ spill_10 (int32_t *in, int32_t *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-4.c index ef61d9a2c0c3..1faf31ffd8e0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-4.c @@ -102,5 +102,5 @@ spill_9 (int64_t *in, int64_t *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c index 150135a91103..0c8dccc518e3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-5.c @@ -120,5 +120,5 @@ spill_11 (_Float16 *in, _Float16 *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c index c5d2d0194348..8bf53b84d1cd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-6.c @@ -111,5 +111,5 @@ spill_10 (float *in, float *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-7.c index 70ca683908db..e3980a295406 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/spill-7.c @@ -102,5 +102,5 @@ spill_9 (int64_t *in, int64_t *out) /* { dg-final { scan-assembler-times {addi\tsp,sp,-256} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-512} 1 } } */ /* { dg-final { scan-assembler-times {addi\tsp,sp,-1024} 1 } } */ -/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 1 } } */ -/* { dg-final { scan-assembler-times {li\t[a-x0-9]+,-4096\s+add\tsp,sp,[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,-2048} 3 } } */ +/* { dg-final { scan-assembler-times {addi\tsp,sp,2032} 1 } } */

[v2,2/2] RISC-V: avoid LUI based const mat in prologue/epilogue expansion [PR/105733]

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