[v1] Internal-fn: Introduce new internal function SAT_ADD

From: Pan Li <pan2.li@intel.com>

From: Pan Li <pan2.li@intel.com>

This patch would like to add the middle-end presentation for the
saturation add.  Aka set the result of add to the max when overflow.
It will take the pattern similar as below.

SAT_ADD (x, y) => (x + y) | (-(TYPE)((TYPE)(x + y) < x))

Take uint8_t as example, we will have:

* SAT_ADD (1, 254)   => 255.
* SAT_ADD (1, 255)   => 255.
* SAT_ADD (2, 255)   => 255.
* SAT_ADD (255, 255) => 255.

The patch also implement the SAT_ADD in the riscv backend as
the sample for both the scalar and vector.  Given below example:

uint64_t sat_add_u64 (uint64_t x, uint64_t y)
{
  return (x + y) | (- (uint64_t)((uint64_t)(x + y) < x));
}

Before this patch:
uint64_t sat_add_uint64_t (uint64_t x, uint64_t y)
{
  long unsigned int _1;
  _Bool _2;
  long unsigned int _3;
  long unsigned int _4;
  uint64_t _7;
  long unsigned int _10;
  __complex__ long unsigned int _11;

;;   basic block 2, loop depth 0
;;    pred:       ENTRY
  _11 = .ADD_OVERFLOW (x_5(D), y_6(D));
  _1 = REALPART_EXPR <_11>;
  _10 = IMAGPART_EXPR <_11>;
  _2 = _10 != 0;
  _3 = (long unsigned int) _2;
  _4 = -_3;
  _7 = _1 | _4;
  return _7;
;;    succ:       EXIT

}

After this patch:
uint64_t sat_add_uint64_t (uint64_t x, uint64_t y)
{
  uint64_t _7;

;;   basic block 2, loop depth 0
;;    pred:       ENTRY
  _7 = .SAT_ADD (x_5(D), y_6(D)); [tail call]
  return _7;
;;    succ:       EXIT
}

For vectorize, we leverage the existing vect pattern recog to find
the pattern similar to scalar and let the vectorizer to perform
the rest part for standard name usadd<mode>3 in vector mode.
The riscv vector backend have insn "Vector Single-Width Saturating
Add and Subtract" which can be leveraged when expand the usadd<mode>3
in vector mode.  For example:

void vec_sat_add_u64 (uint64_t *out, uint64_t *x, uint64_t *y, unsigned n)
{
  unsigned i;

  for (i = 0; i < n; i++)
    out[i] = (x[i] + y[i]) | (- (uint64_t)((uint64_t)(x[i] + y[i]) < x[i]));
}

Before this patch:
void vec_sat_add_u64 (uint64_t *out, uint64_t *x, uint64_t *y, unsigned n)
{
  ...
  _80 = .SELECT_VL (ivtmp_78, POLY_INT_CST [2, 2]);
  ivtmp_58 = _80 * 8;
  vect__4.7_61 = .MASK_LEN_LOAD (vectp_x.5_59, 64B, { -1, ... }, _80, 0);
  vect__6.10_65 = .MASK_LEN_LOAD (vectp_y.8_63, 64B, { -1, ... }, _80, 0);
  vect__7.11_66 = vect__4.7_61 + vect__6.10_65;
  mask__8.12_67 = vect__4.7_61 > vect__7.11_66;
  vect__12.15_72 = .VCOND_MASK (mask__8.12_67, { 18446744073709551615, ... }, vect__7.11_66);
  .MASK_LEN_STORE (vectp_out.16_74, 64B, { -1, ... }, _80, 0, vect__12.15_72);
  vectp_x.5_60 = vectp_x.5_59 + ivtmp_58;
  vectp_y.8_64 = vectp_y.8_63 + ivtmp_58;
  vectp_out.16_75 = vectp_out.16_74 + ivtmp_58;
  ivtmp_79 = ivtmp_78 - _80;
  ...
}

vec_sat_add_u64:
  ...
  vsetvli a5,a3,e64,m1,ta,ma
  vle64.v v0,0(a1)
  vle64.v v1,0(a2)
  slli    a4,a5,3
  sub     a3,a3,a5
  add     a1,a1,a4
  add     a2,a2,a4
  vadd.vv v1,v0,v1
  vmsgtu.vv       v0,v0,v1
  vmerge.vim      v1,v1,-1,v0
  vse64.v v1,0(a0)
  ...

After this patch:
void vec_sat_add_u64 (uint64_t *out, uint64_t *x, uint64_t *y, unsigned n)
{
  ...
  _62 = .SELECT_VL (ivtmp_60, POLY_INT_CST [2, 2]);
  ivtmp_46 = _62 * 8;
  vect__4.7_49 = .MASK_LEN_LOAD (vectp_x.5_47, 64B, { -1, ... }, _62, 0);
  vect__6.10_53 = .MASK_LEN_LOAD (vectp_y.8_51, 64B, { -1, ... }, _62, 0);
  vect__12.11_54 = .SAT_ADD (vect__4.7_49, vect__6.10_53);
  .MASK_LEN_STORE (vectp_out.12_56, 64B, { -1, ... }, _62, 0, vect__12.11_54);
  ...
}

vec_sat_add_u64:
  ...
  vsetvli a5,a3,e64,m1,ta,ma
  vle64.v v1,0(a1)
  vle64.v v2,0(a2)
  slli    a4,a5,3
  sub     a3,a3,a5
  add     a1,a1,a4
  add     a2,a2,a4
  vsaddu.vv       v1,v1,v2
  vse64.v v1,0(a0)
  ...

To limit the patch size for review, only unsigned version of
usadd<mode>3 are involved here. The signed version will be covered
in the underlying patch(es).

The below test suites are passed for this patch.
* The riscv fully regression tests.
* The aarch64 fully regression tests.
* The x86 fully regression tests.

	PR target/51492
	PR target/112600

gcc/ChangeLog:

	* config/riscv/autovec.md (usadd<mode>3): New pattern expand
	for unsigned SAT_ADD vector.
	* config/riscv/riscv-protos.h (riscv_expand_usadd): New func
	decl to expand usadd<mode>3 pattern.
	(expand_vec_usadd): Ditto but for vector.
	* config/riscv/riscv-v.cc (emit_vec_saddu): New func impl to
	emit the vsadd insn.
	(expand_vec_usadd): New func impl to expand usadd<mode>3 for
	vector.
	* config/riscv/riscv.cc (riscv_expand_usadd): New func impl
	to expand usadd<mode>3 for scalar.
	* config/riscv/riscv.md (usadd<mode>3): New pattern expand
	for unsigned SAT_ADD scalar.
	* config/riscv/vector.md: Allow VLS mode for vsaddu.
	* internal-fn.cc (commutative_binary_fn_p): Add type IFN_SAT_ADD.
	* internal-fn.def (SAT_ADD): Add new signed optab SAT_ADD.
	* match.pd: Add unsigned SAT_ADD match and simply.
	* optabs.def (OPTAB_NL): Remove fixed-point limitation for us/ssadd.
	* tree-vect-patterns.cc (vect_sat_add_build_call): New func impl
	to build the IFN_SAT_ADD gimple call.
	(vect_recog_sat_add_pattern): New func impl to recog the pattern
	for unsigned SAT_ADD.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_binary.h: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-2.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-3.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-4.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c: New test.
	* gcc.target/riscv/sat_arith.h: New test.
	* gcc.target/riscv/sat_u_add-1.c: New test.
	* gcc.target/riscv/sat_u_add-2.c: New test.
	* gcc.target/riscv/sat_u_add-3.c: New test.
	* gcc.target/riscv/sat_u_add-4.c: New test.
	* gcc.target/riscv/sat_u_add-run-1.c: New test.
	* gcc.target/riscv/sat_u_add-run-10.c: New test.
	* gcc.target/riscv/sat_u_add-run-11.c: New test.
	* gcc.target/riscv/sat_u_add-run-12.c: New test.
	* gcc.target/riscv/sat_u_add-run-2.c: New test.
	* gcc.target/riscv/sat_u_add-run-3.c: New test.
	* gcc.target/riscv/sat_u_add-run-4.c: New test.
	* gcc.target/riscv/sat_u_add-run-5.c: New test.
	* gcc.target/riscv/sat_u_add-run-6.c: New test.
	* gcc.target/riscv/sat_u_add-run-7.c: New test.
	* gcc.target/riscv/sat_u_add-run-8.c: New test.
	* gcc.target/riscv/sat_u_add-run-9.c: New test.
	* gcc.target/riscv/scalar_sat_binary.h: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/autovec.md                   | 17 ++++
 gcc/config/riscv/riscv-protos.h               |  2 +
 gcc/config/riscv/riscv-v.cc                   | 16 ++++
 gcc/config/riscv/riscv.cc                     | 47 +++++++++++
 gcc/config/riscv/riscv.md                     | 11 +++
 gcc/config/riscv/vector.md                    | 12 +--
 gcc/internal-fn.cc                            |  1 +
 gcc/internal-fn.def                           |  3 +
 gcc/match.pd                                  | 64 +++++++++++++++
 gcc/optabs.def                                |  4 +-
 .../riscv/rvv/autovec/binop/vec_sat_binary.h  | 33 ++++++++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-1.c | 41 ++++++++++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-2.c | 44 +++++++++++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-3.c | 44 +++++++++++
 .../riscv/rvv/autovec/binop/vec_sat_u_add-4.c | 44 +++++++++++
 .../rvv/autovec/binop/vec_sat_u_add-run-1.c   | 75 ++++++++++++++++++
 .../rvv/autovec/binop/vec_sat_u_add-run-10.c  | 75 ++++++++++++++++++
 .../rvv/autovec/binop/vec_sat_u_add-run-11.c  | 75 ++++++++++++++++++
 .../rvv/autovec/binop/vec_sat_u_add-run-12.c  | 75 ++++++++++++++++++
 .../rvv/autovec/binop/vec_sat_u_add-run-2.c   | 75 ++++++++++++++++++
 .../rvv/autovec/binop/vec_sat_u_add-run-3.c   | 75 ++++++++++++++++++
 .../rvv/autovec/binop/vec_sat_u_add-run-4.c   | 75 ++++++++++++++++++
 .../rvv/autovec/binop/vec_sat_u_add-run-5.c   | 75 ++++++++++++++++++
 .../rvv/autovec/binop/vec_sat_u_add-run-6.c   | 75 ++++++++++++++++++
 .../rvv/autovec/binop/vec_sat_u_add-run-7.c   | 75 ++++++++++++++++++
 .../rvv/autovec/binop/vec_sat_u_add-run-8.c   | 75 ++++++++++++++++++
 .../rvv/autovec/binop/vec_sat_u_add-run-9.c   | 75 ++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/sat_arith.h    | 79 +++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/sat_u_add-1.c  | 44 +++++++++++
 gcc/testsuite/gcc.target/riscv/sat_u_add-2.c  | 50 ++++++++++++
 gcc/testsuite/gcc.target/riscv/sat_u_add-3.c  | 41 ++++++++++
 gcc/testsuite/gcc.target/riscv/sat_u_add-4.c  | 38 +++++++++
 .../gcc.target/riscv/sat_u_add-run-1.c        | 25 ++++++
 .../gcc.target/riscv/sat_u_add-run-10.c       | 25 ++++++
 .../gcc.target/riscv/sat_u_add-run-11.c       | 25 ++++++
 .../gcc.target/riscv/sat_u_add-run-12.c       | 25 ++++++
 .../gcc.target/riscv/sat_u_add-run-2.c        | 25 ++++++
 .../gcc.target/riscv/sat_u_add-run-3.c        | 25 ++++++
 .../gcc.target/riscv/sat_u_add-run-4.c        | 25 ++++++
 .../gcc.target/riscv/sat_u_add-run-5.c        | 25 ++++++
 .../gcc.target/riscv/sat_u_add-run-6.c        | 25 ++++++
 .../gcc.target/riscv/sat_u_add-run-7.c        | 25 ++++++
 .../gcc.target/riscv/sat_u_add-run-8.c        | 25 ++++++
 .../gcc.target/riscv/sat_u_add-run-9.c        | 25 ++++++
 .../gcc.target/riscv/scalar_sat_binary.h      | 27 +++++++
 gcc/tree-vect-patterns.cc                     | 61 ++++++++++++++
 46 files changed, 1915 insertions(+), 8 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_binary.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-9.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_arith.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-5.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-6.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-7.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-8.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_add-run-9.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/scalar_sat_binary.h

Message ID	20240406120755.2692291-1-pan2.li@intel.com
State	New
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a="18461762" X-IronPort-AV: E=Sophos;i="6.07,183,1708416000"; d="scan'208";a="18461762" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2024 05:08:07 -0700 X-CSE-ConnectionGUID: /bRHB2/kSqqVm3jl0BxgeQ== X-CSE-MsgGUID: AkDv5VNmRDG+ykqOowskAw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,183,1708416000"; d="scan'208";a="24052007" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa004.fm.intel.com with ESMTP; 06 Apr 2024 05:07:58 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 9E0461005693; Sat, 6 Apr 2024 20:07:57 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, yanzhang.wang@intel.com, tamar.christina@arm.com, richard.guenther@gmail.com, hongtao.liu@intel.com, Pan Li <pan2.li@intel.com> Subject: [PATCH v1] Internal-fn: Introduce new internal function SAT_ADD Date: Sat, 6 Apr 2024 20:07:55 +0800 Message-Id: <20240406120755.2692291-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-9.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_DNSWL_LOW, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_35_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org
Series	[v1] Internal-fn: Introduce new internal function SAT_ADD \| expand [v1] Internal-fn: Introduce new internal function SAT_ADD [v4,2/3] VECT: Support new IFN SAT_ADD for unsigned vector int [v4,3/3] RISC-V: Implement IFN SAT_ADD for both the scalar and vector

[v1] Internal-fn: Introduce new internal function SAT_ADD

Commit Message

Patch