diff mbox series

[v1] RISC-V: Allow RVV intrinsic for more function target

Message ID 20240327031603.453410-1-pan2.li@intel.com
State New
Headers show
Series [v1] RISC-V: Allow RVV intrinsic for more function target | expand

Commit Message

Li, Pan2 March 27, 2024, 3:16 a.m. UTC 
From: Pan Li <pan2.li@intel.com>

In previous, we allowed the target(("arch=+v")) for a function with
rv64gc build.  This patch would like to support more arch options as
below:
* zve32x
* zve32f
* zve64x
* zve64f
* zve64d
* zvfhmin
* zvfh

For example, we have sample code as below.
vfloat32m1_t
__attribute__((target("arch=+zve64f")))
test_9 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
{
  return __riscv_vfadd_vv_f32m1 (a, b, vl);
}

It will generate the asm code when build with -O3 -march=rv64gc
test_9:
        vsetvli zero,a0,e32,m1,ta,ma
        vfadd.vv        v8,v8,v9
        ret

Meanwhile, this patch introduces more error handling for the target
attribute.  Take arch=+zve32x with vfloat32m1_t will have error message
"'vfloat32m1_t' requires the zve32f, zve64f or zve64d ISA extension".
And take arch=+zve32f with vfloat16m1_t will have error message
"'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension".

Below test are passed for this patch:
* The riscv fully regression test.

gcc/ChangeLog:

	* config/riscv/riscv-c.cc (riscv_pragma_intrinsic): Add INT and
	FP vector element flags, invoke override option and mode adjust.
	* config/riscv/riscv-protos.h (riscv_option_override): New extern
	func decl.
	* config/riscv/riscv-vector-builtins.cc (expand_builtin): Return
	target rtx after error_at.
	* config/riscv/riscv.cc (riscv_vector_int_type_p): New predicate
	func to tell one tree type is integer or not.
	(riscv_vector_float_type_p): New predicate func to tell one tree
	type is float or not.
	(riscv_vector_element_bitsize): New func to get the element bitsize
	of a vector tree type.
	(riscv_validate_vector_type): New func to validate the tree type
	is valid on flags.
	(riscv_return_value_is_vector_type_p): Leverage the func
	riscv_validate_vector_type to do the tree type validation.
	(riscv_arguments_is_vector_type_p): Diito.
	(riscv_override_options_internal): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-10.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-11.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-12.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-13.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-14.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-15.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-16.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c: New test.
	* gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-9.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
---
 gcc/config/riscv/riscv-c.cc                   |  30 +++++-
 gcc/config/riscv/riscv-protos.h               |   1 +
 gcc/config/riscv/riscv-vector-builtins.cc     |   7 +-
 gcc/config/riscv/riscv.cc                     | 101 ++++++++++++++++--
 .../target_attribute_v_with_intrinsic-10.c    |  12 +++
 .../target_attribute_v_with_intrinsic-11.c    |  26 +++++
 .../target_attribute_v_with_intrinsic-12.c    |  33 ++++++
 .../target_attribute_v_with_intrinsic-13.c    |  33 ++++++
 .../target_attribute_v_with_intrinsic-14.c    |  40 +++++++
 .../target_attribute_v_with_intrinsic-15.c    |  47 ++++++++
 .../target_attribute_v_with_intrinsic-16.c    |  12 +++
 .../target_attribute_v_with_intrinsic-17.c    |  13 +++
 .../target_attribute_v_with_intrinsic-18.c    |  13 +++
 .../target_attribute_v_with_intrinsic-19.c    |  13 +++
 .../target_attribute_v_with_intrinsic-20.c    |  13 +++
 .../target_attribute_v_with_intrinsic-21.c    |  13 +++
 .../target_attribute_v_with_intrinsic-22.c    |  13 +++
 .../target_attribute_v_with_intrinsic-23.c    |  13 +++
 .../target_attribute_v_with_intrinsic-24.c    |  13 +++
 .../target_attribute_v_with_intrinsic-25.c    |  13 +++
 .../target_attribute_v_with_intrinsic-26.c    |  13 +++
 .../target_attribute_v_with_intrinsic-27.c    |  13 +++
 .../target_attribute_v_with_intrinsic-28.c    |  13 +++
 .../target_attribute_v_with_intrinsic-29.c    |  13 +++
 .../target_attribute_v_with_intrinsic-9.c     |  12 +++
 25 files changed, 511 insertions(+), 12 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-11.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-12.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-13.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-14.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-15.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-16.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-9.c

Comments

Kito Cheng March 28, 2024, 6:43 a.m. UTC | #1 
Just tried something interesting:

$ riscv64-unknown-linux-gnu-gcc -march=rv64gc -O
target_attribute_v_with_intrinsic-9.c -S # Work
$ riscv64-unknown-linux-gnu-gcc -march=rv64gc_zve32x -O
target_attribute_v_with_intrinsic-9.c -S # Not work

Also I guess all zvk* and zvbb may also need to be added as well,
but...I suspect it's not scalable way?
Li, Pan2 March 28, 2024, 7:32 a.m. UTC | #2 
Thanks kito, looks missed this part in test, let me check it out.

Pan

-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com> 
Sent: Thursday, March 28, 2024 2:44 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Allow RVV intrinsic for more function target

Just tried something interesting:

$ riscv64-unknown-linux-gnu-gcc -march=rv64gc -O
target_attribute_v_with_intrinsic-9.c -S # Work
$ riscv64-unknown-linux-gnu-gcc -march=rv64gc_zve32x -O
target_attribute_v_with_intrinsic-9.c -S # Not work

Also I guess all zvk* and zvbb may also need to be added as well,
but...I suspect it's not scalable way?
Li, Pan2 March 28, 2024, 7:52 a.m. UTC | #3 
I see. This failure comes from that we have zve32x (TARGET_VECTOR is true) in command line, and then we don't do the reinit in riscv_pragma_intrinsic in v1.

As I understand, we need something like below, no matter TARGET_VECTOR is true or false.

Int flags_backup = flags;
Int new_flags = flags | ...;

reinit ();

flags = flags_backup ();
reinit ();

> Also I guess all zvk* and zvbb may also need to be added as well,
> but...I suspect it's not scalable way?

If zvk* and zvbb doesn't introduce new modes, I suspect we don't need to add here, let me double check about it and update in v2.

Pan

-----Original Message-----
From: Li, Pan2 <pan2.li@intel.com> 
Sent: Thursday, March 28, 2024 3:32 PM
To: Kito Cheng <kito.cheng@gmail.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: RE: [PATCH v1] RISC-V: Allow RVV intrinsic for more function target

Thanks kito, looks missed this part in test, let me check it out.

Pan

-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com> 
Sent: Thursday, March 28, 2024 2:44 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Allow RVV intrinsic for more function target

Just tried something interesting:

$ riscv64-unknown-linux-gnu-gcc -march=rv64gc -O
target_attribute_v_with_intrinsic-9.c -S # Work
$ riscv64-unknown-linux-gnu-gcc -march=rv64gc_zve32x -O
target_attribute_v_with_intrinsic-9.c -S # Not work

Also I guess all zvk* and zvbb may also need to be added as well,
but...I suspect it's not scalable way?
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 01314037461..62405ef0004 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -207,13 +207,39 @@  riscv_pragma_intrinsic (cpp_reader *)
 	{
 	  /* To make the the rvv types and intrinsic API available for the
 	     target("arch=+v") attribute,  we need to temporally enable the
-	     TARGET_VECTOR, and disable it after all initialized.  */
+	     related flags, and disable it after all initialized.  */
 	  target_flags |= MASK_VECTOR;
-
+	  riscv_vector_elen_flags = riscv_vector_elen_flags
+	   | MASK_VECTOR_ELEN_32
+	   | MASK_VECTOR_ELEN_64
+	   | MASK_VECTOR_ELEN_FP_16
+	   | MASK_VECTOR_ELEN_FP_32
+	   | MASK_VECTOR_ELEN_FP_64;
+	  riscv_zvl_flags = riscv_zvl_flags
+	   | MASK_ZVL32B
+	   | MASK_ZVL64B
+	   | MASK_ZVL128B;
+
+	  riscv_option_override ();
+	  init_adjust_machine_modes ();
 	  riscv_vector::init_builtins ();
 	  riscv_vector::handle_pragma_vector ();
 
 	  target_flags &= ~MASK_VECTOR;
+	  riscv_vector_elen_flags = riscv_vector_elen_flags
+	   & ~MASK_VECTOR_ELEN_32
+	   & ~MASK_VECTOR_ELEN_64
+	   & ~MASK_VECTOR_ELEN_FP_16
+	   & ~MASK_VECTOR_ELEN_FP_32
+	   & ~MASK_VECTOR_ELEN_FP_64;
+	  riscv_zvl_flags = riscv_zvl_flags
+	   & ~MASK_ZVL32B
+	   & ~MASK_ZVL64B
+	   & ~MASK_ZVL128B;
+
+	  /* Re-initialize after the flags are restored.  */
+	  riscv_option_override ();
+	  init_adjust_machine_modes ();
 	}
     }
   else
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index b8735593805..fc65f0c6c8a 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -762,6 +762,7 @@  extern bool
 riscv_option_valid_attribute_p (tree, tree, tree, int);
 extern void
 riscv_override_options_internal (struct gcc_options *);
+extern void riscv_option_override (void);
 
 struct riscv_tune_param;
 /* Information about one micro-arch we know about.  */
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index e07373d8b57..85a575d3749 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -4588,8 +4588,11 @@  expand_builtin (unsigned int code, tree exp, rtx target)
   registered_function &rfn = *(*registered_functions)[code];
 
   if (!TARGET_VECTOR)
-    error_at (EXPR_LOCATION (exp),
-	      "builtin function %qE requires the V ISA extension", exp);
+    {
+      error_at (EXPR_LOCATION (exp),
+		"builtin function %qE requires the V ISA extension", exp);
+      return target;
+    }
 
   return function_expander (rfn.instance, rfn.decl, exp, target).expand ();
 }
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index fe9976bfffe..5a1b24af949 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5459,6 +5459,96 @@  riscv_v_abi ()
   return v_abi;
 }
 
+static bool
+riscv_vector_int_type_p (const_tree type)
+{
+  const char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type)));
+
+  return strstr (name, "vint") != NULL || strstr (name, "vuint") != NULL;
+}
+
+static bool
+riscv_vector_float_type_p (const_tree type)
+{
+  const char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type)));
+
+  return strstr (name, "vfloat") != NULL;
+}
+
+static unsigned
+riscv_vector_element_bitsize (const_tree type)
+{
+  const char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type)));
+
+  if (strstr (name, "bool") != NULL)
+    return 1;
+  if (strstr (name, "int8") != NULL)
+    return 8;
+  else if (strstr (name, "int16") != NULL || strstr (name, "float16") != NULL)
+    return 16;
+  else if (strstr (name, "int32") != NULL || strstr (name, "float32") != NULL)
+    return 32;
+  else if (strstr (name, "int64") != NULL || strstr (name, "float64") != NULL)
+    return 64;
+
+  gcc_unreachable ();
+}
+
+static void
+riscv_validate_vector_type (const_tree type, const char *hint)
+{
+  gcc_assert (riscv_vector_type_p (type));
+
+  if (VECTOR_MODE_P (TYPE_MODE (type)))
+    return;
+
+  if (!TARGET_VECTOR)
+    {
+      error_at (input_location, "%s %qT requires the V ISA extension",
+		hint, type);
+      return;
+    }
+
+  unsigned element_bitsize = riscv_vector_element_bitsize (type);
+  bool int_type_p = riscv_vector_int_type_p (type);
+  bool float_type_p = riscv_vector_float_type_p (type);
+
+  if (int_type_p && element_bitsize == 64
+    && !TARGET_VECTOR_ELEN_64_P (riscv_vector_elen_flags))
+    {
+      error_at (input_location,
+		"%s %qT requires the zve64x, zve64f or zve64d ISA extension",
+		hint, type);
+      return;
+    }
+
+  if (float_type_p && element_bitsize == 16
+    && !TARGET_VECTOR_ELEN_FP_16_P (riscv_vector_elen_flags))
+    {
+      error_at (input_location,
+		"%s %qT requires the zvfhmin or zvfh ISA extension",
+		hint, type);
+      return;
+    }
+
+  if (float_type_p && element_bitsize == 32
+    && !TARGET_VECTOR_ELEN_FP_32_P (riscv_vector_elen_flags))
+    {
+      error_at (input_location,
+		"%s %qT requires the zve32f, zve64f or zve64d ISA extension",
+		hint, type);
+      return;
+    }
+
+  if (float_type_p && element_bitsize == 64
+    && !TARGET_VECTOR_ELEN_FP_64_P (riscv_vector_elen_flags))
+    {
+      error_at (input_location,
+		"%s %qT requires the zve64d ISA extension", hint, type);
+      return;
+    }
+}
+
 /* Return true if a function with type FNTYPE returns its value in
    RISC-V V registers.  */
 
@@ -5469,9 +5559,7 @@  riscv_return_value_is_vector_type_p (const_tree fntype)
 
   if (riscv_vector_type_p (return_type))
     {
-      if (!TARGET_VECTOR)
-	error_at (input_location,
-		  "return type %qT requires the V ISA extension", return_type);
+      riscv_validate_vector_type (return_type, "return type");
       return true;
     }
   else
@@ -5490,10 +5578,7 @@  riscv_arguments_is_vector_type_p (const_tree fntype)
       tree arg_type = TREE_VALUE (chain);
       if (riscv_vector_type_p (arg_type))
 	{
-	  if (!TARGET_VECTOR)
-	    error_at (input_location,
-		      "argument type %qT requires the V ISA extension",
-		      arg_type);
+	  riscv_validate_vector_type (arg_type, "argument type");
 	  return true;
 	}
     }
@@ -9107,7 +9192,7 @@  riscv_override_options_internal (struct gcc_options *opts)
 
 /* Implement TARGET_OPTION_OVERRIDE.  */
 
-static void
+void
 riscv_option_override (void)
 {
 #ifdef SUBTARGET_OVERRIDE_OPTIONS
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-10.c
new file mode 100644
index 00000000000..3e6844475d5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-10.c
@@ -0,0 +1,12 @@ 
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16m1_t
+__attribute__((target("arch=+v,+zvfh")))
+test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f16m1 (a, b, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-11.c
new file mode 100644
index 00000000000..df053073bc8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-11.c
@@ -0,0 +1,26 @@ 
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vint8m1_t
+__attribute__((target("arch=+zve32x")))
+test_1 (vint8m1_t a, vint8m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i8m1 (a, b, vl);
+}
+
+vint16m1_t
+__attribute__((target("arch=+zve32x")))
+test_2 (vint16m1_t a, vint16m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i16m1 (a, b, vl);
+}
+
+vint32m1_t
+__attribute__((target("arch=+zve32x")))
+test_3 (vint32m1_t a, vint32m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i32m1 (a, b, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-12.c
new file mode 100644
index 00000000000..51a91886f52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-12.c
@@ -0,0 +1,33 @@ 
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vint8m1_t
+__attribute__((target("arch=+zve32f")))
+test_1 (vint8m1_t a, vint8m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i8m1 (a, b, vl);
+}
+
+vint16m1_t
+__attribute__((target("arch=+zve32f")))
+test_2 (vint16m1_t a, vint16m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i16m1 (a, b, vl);
+}
+
+vint32m1_t
+__attribute__((target("arch=+zve32f")))
+test_3 (vint32m1_t a, vint32m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i32m1 (a, b, vl);
+}
+
+vfloat32m1_t
+__attribute__((target("arch=+zve32f")))
+test_4 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f32m1 (a, b, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-13.c
new file mode 100644
index 00000000000..994b1c0a5db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-13.c
@@ -0,0 +1,33 @@ 
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vint8m1_t
+__attribute__((target("arch=+zve64x")))
+test_1 (vint8m1_t a, vint8m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i8m1 (a, b, vl);
+}
+
+vint16m1_t
+__attribute__((target("arch=+zve64x")))
+test_2 (vint16m1_t a, vint16m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i16m1 (a, b, vl);
+}
+
+vint32m1_t
+__attribute__((target("arch=+zve64x")))
+test_3 (vint32m1_t a, vint32m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i32m1 (a, b, vl);
+}
+
+vint64m1_t
+__attribute__((target("arch=+zve64x")))
+test_4 (vint64m1_t a, vint64m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i64m1 (a, b, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-14.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-14.c
new file mode 100644
index 00000000000..caa2a10e943
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-14.c
@@ -0,0 +1,40 @@ 
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vint8m1_t
+__attribute__((target("arch=+zve64f")))
+test_1 (vint8m1_t a, vint8m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i8m1 (a, b, vl);
+}
+
+vint16m1_t
+__attribute__((target("arch=+zve64f")))
+test_2 (vint16m1_t a, vint16m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i16m1 (a, b, vl);
+}
+
+vint32m1_t
+__attribute__((target("arch=+zve64f")))
+test_3 (vint32m1_t a, vint32m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i32m1 (a, b, vl);
+}
+
+vint64m1_t
+__attribute__((target("arch=+zve64f")))
+test_4 (vint64m1_t a, vint64m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i64m1 (a, b, vl);
+}
+
+vfloat32m1_t
+__attribute__((target("arch=+zve64f")))
+test_5 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f32m1 (a, b, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-15.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-15.c
new file mode 100644
index 00000000000..72a2be6e560
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-15.c
@@ -0,0 +1,47 @@ 
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vint8m1_t
+__attribute__((target("arch=+zve64d")))
+test_1 (vint8m1_t a, vint8m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i8m1 (a, b, vl);
+}
+
+vint16m1_t
+__attribute__((target("arch=+zve64d")))
+test_2 (vint16m1_t a, vint16m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i16m1 (a, b, vl);
+}
+
+vint32m1_t
+__attribute__((target("arch=+zve64d")))
+test_3 (vint32m1_t a, vint32m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i32m1 (a, b, vl);
+}
+
+vint64m1_t
+__attribute__((target("arch=+zve64d")))
+test_4 (vint64m1_t a, vint64m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i64m1 (a, b, vl);
+}
+
+vfloat32m1_t
+__attribute__((target("arch=+zve64d")))
+test_5 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f32m1 (a, b, vl);
+}
+
+vfloat64m1_t
+__attribute__((target("arch=+zve64d")))
+test_6 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f64m1 (a, b, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-16.c
new file mode 100644
index 00000000000..dabdcf8ff21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-16.c
@@ -0,0 +1,12 @@ 
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat32m1_t
+__attribute__((target("arch=+v,+zvfhmin")))
+test_1 (vfloat16mf2_t a, size_t vl)
+{
+  return __riscv_vfwcvt_f_f_v_f32m1 (a, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
new file mode 100644
index 00000000000..daabe88cd25
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-17.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t
+__attribute__((target("arch=+zve32x")))
+test_1 (vint64m1_t a, vint64m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i64m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vint64m1_t' requires the zve64x, zve64f or zve64d ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
new file mode 100644
index 00000000000..4461bfd7412
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-18.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat32m1_t
+__attribute__((target("arch=+zve32x")))
+test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f32m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat32m1_t' requires the zve32f, zve64f or zve64d ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c
new file mode 100644
index 00000000000..bfc26f8210a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-19.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16m1_t
+__attribute__((target("arch=+zve32x")))
+test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f16m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c
new file mode 100644
index 00000000000..27a3bf7ea82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-20.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat64m1_t
+__attribute__((target("arch=+zve32x")))
+test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f64m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat64m1_t' requires the zve64d ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c
new file mode 100644
index 00000000000..4aaccdd96f3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-21.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vint64m1_t
+__attribute__((target("arch=+zve32f")))
+test_1 (vint64m1_t a, vint64m1_t b, size_t vl)
+{
+  return __riscv_vadd_vv_i64m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vint64m1_t' requires the zve64x, zve64f or zve64d ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c
new file mode 100644
index 00000000000..b5a894ecad4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-22.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16m1_t
+__attribute__((target("arch=+zve32f")))
+test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f16m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c
new file mode 100644
index 00000000000..f98ebc4dd9f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-23.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat64m1_t
+__attribute__((target("arch=+zve32f")))
+test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f64m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat64m1_t' requires the zve64d ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c
new file mode 100644
index 00000000000..438f2ea7125
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-24.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat32m1_t
+__attribute__((target("arch=+zve64x")))
+test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f32m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat32m1_t' requires the zve32f, zve64f or zve64d ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c
new file mode 100644
index 00000000000..f1241cb1771
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-25.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16m1_t
+__attribute__((target("arch=+zve64x")))
+test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f16m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c
new file mode 100644
index 00000000000..4852bfbd154
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-26.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat64m1_t
+__attribute__((target("arch=+zve64x")))
+test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f64m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat64m1_t' requires the zve64d ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c
new file mode 100644
index 00000000000..c2e9490e7d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-27.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat64m1_t
+__attribute__((target("arch=+zve64f")))
+test_1 (vfloat64m1_t a, vfloat64m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f64m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat64m1_t' requires the zve64d ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c
new file mode 100644
index 00000000000..7eaa6adab82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-28.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16m1_t
+__attribute__((target("arch=+zve64f")))
+test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f16m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c
new file mode 100644
index 00000000000..eb74e33299f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-29.c
@@ -0,0 +1,13 @@ 
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat16m1_t
+__attribute__((target("arch=+zve64d")))
+test_1 (vfloat16m1_t a, vfloat16m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f16m1 (a, b, vl);
+}
+
+/* { dg-error "return type 'vfloat16m1_t' requires the zvfhmin or zvfh ISA extension" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-9.c
new file mode 100644
index 00000000000..0764f403b89
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-9.c
@@ -0,0 +1,12 @@ 
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+vfloat32m1_t
+__attribute__((target("arch=+v")))
+test_1 (vfloat32m1_t a, vfloat32m1_t b, size_t vl)
+{
+  return __riscv_vfadd_vv_f32m1 (a, b, vl);
+}