Message ID | 20231221022518.4175834-1-pan2.li@intel.com |
---|---|
State | New |
Headers | show |
Series | [v1] RISC-V: XFail the signbit-5 run test for RVV | expand |
On 12/20/23 19:25, pan2.li@intel.com wrote: > From: Pan Li <pan2.li@intel.com> > > This patch would like to XFail the signbit-5 run test case for > the RVV. Given the case has one limitation like "This test does not > work when the truth type does not match vector type." in the beginning > of the test file. Aka, the RVV vector truth type is not integer type. > > The target board of riscv-sim like below will pick up `-march=rv64gcv` > when building the run test elf. Thus, the RVV cannot bypass this test > case like aarch64_sve with additional option `-march=armv8-a`. > > riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow > > For RVV, we leverage dg-xfail-run-if for this case like `amdgcn`. But isn't that just going to turn this into an XPASS when vector is not enabled? Looking at a recent rv64gc run of mine: > PASS: gcc.dg/signbit-5.c (test for excess errors) > PASS: gcc.dg/signbit-5.c execution test Ideally we'd find a way to handle with and without vector. jeff
Maybe use riscv_v ? juzhe.zhong@rivai.ai From: Jeff Law Date: 2023-12-22 03:16 To: pan2.li; gcc-patches CC: juzhe.zhong; yanzhang.wang; kito.cheng; richard.guenther; tamar.christina Subject: Re: [PATCH v1] RISC-V: XFail the signbit-5 run test for RVV On 12/20/23 19:25, pan2.li@intel.com wrote: > From: Pan Li <pan2.li@intel.com> > > This patch would like to XFail the signbit-5 run test case for > the RVV. Given the case has one limitation like "This test does not > work when the truth type does not match vector type." in the beginning > of the test file. Aka, the RVV vector truth type is not integer type. > > The target board of riscv-sim like below will pick up `-march=rv64gcv` > when building the run test elf. Thus, the RVV cannot bypass this test > case like aarch64_sve with additional option `-march=armv8-a`. > > riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow > > For RVV, we leverage dg-xfail-run-if for this case like `amdgcn`. But isn't that just going to turn this into an XPASS when vector is not enabled? Looking at a recent rv64gc run of mine: > PASS: gcc.dg/signbit-5.c (test for excess errors) > PASS: gcc.dg/signbit-5.c execution test Ideally we'd find a way to handle with and without vector. jeff
Thanks all for comments, will have a try for riscv_v and send V2 if everything goes well.
Pan
From: 钟居哲 <juzhe.zhong@rivai.ai>
Sent: Friday, December 22, 2023 6:44 AM
To: Jeff Law <jeffreyalaw@gmail.com>; Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>; richard.guenther <richard.guenther@gmail.com>; Tamar Christina <tamar.christina@arm.com>
Subject: Re: Re: [PATCH v1] RISC-V: XFail the signbit-5 run test for RVV
Maybe use riscv_v ?
diff --git a/gcc/testsuite/gcc.dg/signbit-5.c b/gcc/testsuite/gcc.dg/signbit-5.c index 0fad56c0ea8..e358d23a192 100644 --- a/gcc/testsuite/gcc.dg/signbit-5.c +++ b/gcc/testsuite/gcc.dg/signbit-5.c @@ -5,6 +5,7 @@ /* { dg-additional-options "-mno-avx512f" { target { i?86-*-* x86_64-*-* } } } */ /* { dg-additional-options "-march=armv8-a" { target aarch64_sve } } */ /* { dg-xfail-run-if "truth type does not match vector type" { amdgcn-*-* } } */ +/* { dg-xfail-run-if "truth type does not match vector type" { riscv*-*-* } } */ #include <stdint.h>