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[3/3,RFC] RISC-V: Enable assert for insn_has_dfa_reservation

Message ID 20231215185328.794425-4-ewlu@rivosinc.com
State New
Headers show
Series RISC-V: Associate typed insns to dfa reservation | expand

Commit Message

Edwin Lu Dec. 15, 2023, 6:53 p.m. UTC 
Enables assert that every typed instruction is associated with a
dfa reservation

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
 gcc/config/riscv/riscv.cc | 2 --
 1 file changed, 2 deletions(-)

Comments

Jeff Law Dec. 20, 2023, 6:57 p.m. UTC | #1 
On 12/15/23 11:53, Edwin Lu wrote:
> Enables assert that every typed instruction is associated with a
> dfa reservation
> 
> gcc/ChangeLog:
> 
> 	* config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
Once the prereqs are in, this is fine.
jeff
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ab0f95e5fe9..3adeb415bec 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8048,9 +8048,7 @@  riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, int more)
 
   /* If we ever encounter an insn without an insn reservation, trip
      an assert so we can find and fix this problem.  */
-#if 0
   gcc_assert (insn_has_dfa_reservation_p (insn));
-#endif
 
   return more - 1;
 }